Current version

r4B45

Status

Completed, ready for production

PCB manufactured

Yes (r4B43a 08/2015)

PCB assembled

Yes (r4B43a 08/2015)

BOM

Yes (Farnell, TME)

File repository

https://github.com/eez-open/psu-hw/releases/tag/1.0

(include Eagle, Gerber, BOM files and SPICE simulations)

License

TAPR v1.0

Revision history

2016-03-27 r4B45

  • Battery NTC V/F input replaced with SET_100% output required for SMPS pre-regulator based on LTC3864

2015-11-10 r4B44 – first public release

 

Fig. 1: Post-regulator module assembled (r4B43a)

 

The post-regulator module is inspired by exceptional work of Leonid Ivanovitch that is presented on the EEVblog forum. Major difference between Leonid’s work and this design is based in the selection of main transformer’s multiple tap secondary winding versus single tap. Lack of multiple tap requires pre-regulator as a mean of lowering the input and output voltage on the post-regulator.

The connection between pre-regulator and post-regulator module is accomplished with a single 18-pin connector (X2) that is used to deliver variable power output (few volts above programmed output voltage), power mosfet bias voltage output, bias power outputs for analog and digital sections. Post-regulator output voltage is also present on this connector (X2-9) as an input that is used for programming pre-regulator output voltage.

Despite the fact that four pins are used for power lines that even in case of 5 A setup put reasonable load of 800 mA per pin it’s highly recommended to use known brand connector with specified max. current. It’s quite possible that some of low-cost variants could not safely carry such load for extended period of time that can results in mechanical damages such as isolation melting due to overheating.

 

Fig. 2: CV and CC control loops, serial mosfet driver, OE, DP

Series/pass element and control loops

The N-channel mosfet (Q1) connected as common drain is used as series regulator. There is many possible mosfets that could be used for Q1 and it has to be carefully selected to not compromise its SOA for the desired output voltage and current range. Q1 requires for normal operation a bias voltage applied on its gate that is few volts above drain voltage. Usually for that purpose an additional bias power source derived from auxiliary secondary transformer winding or charge pump is employed. The output of such power source is floating on top of drain voltage since its negative output is connected to the drain voltage ensuring constant difference between gate and drain potential regardless of the input voltage (applied to the drain). Instead of dedicated gate bias supply we are using rectified voltage from main transformer that are present on the pre-regulator’s input. The pre-regulator that resides between that voltage and Q1 drain (post-regulator input) ensure that regardless of programmed output voltage. For example if 40 VAC main transformer is used, rectified voltage on the pre-regulator’s input will be max. 57 V and pre-regulator output could be 3 to 43 V depending of programmed output voltage. That gives us difference from 54 to 14 V that could be used for gate bias. That difference is not constant and that put some more load on Q4 but it’s dimensioned for that and for heat dissipation a small cooper area of the top PCB layer is used. The zener diode ZD1 insures that gate-source voltage (Vgs) stays within allowed limits (i.e. below 20 V).

Diode D1 protects Q4 from B-E junction breakdown and D2 (the same is with D4) is added to prevent current flowing from the external source when output is switched off.

Output voltage on Q1 that is controlled with two control loops: Constant Voltage (IC1) and Constant Current (IC2, IC3) and in general only one of them could be active at the time. Diodes D5 and D7 ensures that output signal from one control loop do not affect the other loop functionality. Q9 is common base voltage amplifier stage and R8 and R18 forms local negative feedback.

Both control loops are using the same precise voltage reference REF5025 (IC7, Fig. 7) for programming output voltage and current. The voltage reference output is 2.5 V. Therefore gain of both control loop has to be adjusted in a way that output range returns positive value between zero and 2.5 V. That is accomplished by selecting feedback loop resistors of IC1B and IC3 that are connected as differential amplifiers. For example if we’d like to have output voltage in the range from zero to 50 V the IC1B gain has to be 2.5 / 50 = 0.05 (actually the output signal has to be attenuated 20 times).

Output voltage could be “sensed” locally or remotely. In former case inputs X1-3 and X1-4 has to be connected to the power output pins (X1-1, X1-2) and in the later case such connection is accomplished on the load’s input terminals using twisted pair cable. Remote sensing cable could be also shielded when cable shield has to the connected on the protective earth terminal only on the one end to avoid creation of the ground loop.

The output current is measured as a voltage drop on the current sense resistor (R40) and current range can be also defined by changing the value of that resistor – higher value will produce the higher voltage drop for the same current and therefore IC3 gain could be smaller. In that way we could improve precision of the measured value, but from other side using the value that is too high could produce excessive heating of the current sense resistor since the dissipated power rise with the square of the current.

It is important to take into account that heating of the current sense resistor decrease accuracy because its resistance is temperature dependent. Choosing a resistor with low TCR while keeping dissipation low gives the best results.

With selected value of 20 mΩ and max. current of 5 A dissipated power will be only 100 mW that is acceptable for selected power rate of 2 W. Tables in the lower left corner on Fig. 2 contains required values for feedback loop resistors for the following ranges:

 

Range

Required gain

0 – 30 V

0.8333 (5/6)

0 – 40 V

0.625 (5/8)

0 – 50 V

0.05 (1/20)

0 – 3.12 A

40 (R40 = 20 mΩ)

0 – 5 A

25 (R40 = 20 mΩ)

 

Since voltage and current are programmed separately and combination of output current and voltage is possible that give us in this case six variations. That also mean that dual channel power supply if required could be build with two different output ranges (e.g. 0 – 40 V / 5 A and 0 – 50 V / 3.12 A).

Output enable (OE) and down-programmer (DP)

Two important functionality that are located on the post-regulator module are output enable and down-programmer. Output enable is a two-state circuit for enabling power output and quick disabling it in the case of emergency (e.g. connected load is start to overheat because of erroneously programmed voltage and current levels). Output enable circuit consists of Q7, Q8 current mirror controlled by Q10 and Q11 (Fig. 6) that regulate bias voltage that is delivered by Q4 to Q1.

The down-programmer circuit is built using Q5, Q2 that are controlled by Q6, Q12 (Fig. 6). It’s improving programming output voltage fall time (hence the name down programmer).

Thanks to it the fall time (from previously programmed higher voltage to the newly programmed lower voltage) could be for the order of magnitude shorter in comparison with power supplies that do not have regardless of how small is power supply’s output capacitor since it could actively sink power stored in mentioned power supply’s output capacitor (in our case C1, C2) but also input capacitor that could exist on the connected load or device.

Fig. 3 and Fig. 4 shows the difference in programmed output step from 20 to 0 V with and without down-programmer circuit activated.

Fig. 3: Output voltage with DP enabled

 

Fig. 4: Output voltage with DP disabled

The common practice is that down-programmer follows the state of the output enable circuit: it is enabled when output is enabled and vice versa. The down-programmer circuit of this post-regulator module could be controlled independently if required and its default state is on, therefore DP control circuit will be disabled when 5 V is applied to its input (SET_DP signal).

The down-programmer has a finite sinking capability that is set to approx. 300 mA (limited with R2). That starts to be visible when device with huge capacitor (or such capacitor alone) is connected to the post-regulator output. Fig. shows fall time of ~150 ms with 1 000 μF capacitor charged to 50 V.

 

Fig. 5: Output voltage fall time from 50 to 0 V with 1 000 μF

CC/CV comparators

Power supply when output is enabled could work in one of the following mode of operation:

  • CV (constant voltage) when voltage control loop (IC1) is controlling the output. This mode is assumed as default for power supplies with series regulator element.
  • CC (constant current) when current control loop (IC2, IC3) take over output control and
  • UR (unregulated or not regulated) when neither (or even both) of above mentioned control loop are controlling the output. Unregulated state can occur when the input voltage is not high enough, for example, due to decreased mains voltage, or external voltage is applied to the output that is above the programmed value.

CC and CV circuits (Fig. 6) uses “window comparators” that requires two comparators to detect lower and upper voltage level. CV signal is generated by comparing U_SERVO output from IC1A using IC4B, IC4A as window comparator. In the same fashion CC signal use I_SERVO output from IC2 and IC4D, IC4C comparators. Generated signals are level shifted for TTL inputs (R53, R55 and R60, R62 voltage dividers). They could be also optionally buffered for driving LEDs using small signal mosfets Q13, Q14.

 

Fig. 6: CC/CV comparators and optional manual control

Output programming

Post-regulator is an analog circuit controlled by control loops that are also analog. Therefore any function that we want to accomplish digitally using e.g. MCU will require some kind of signal conversion. For that purpose the following three devices are added on board (see Fig. 7):

  • DAC8552 dual channel 16-bit Digital to analog converter (IC6),
  • ADS1120 15-bit delta-sigma (ΔΣ) analog to digital converter (IC8) and
  • MCP23S08 8-bit I/O expander (IC5)

IMPORTANT: All digital devices are powered with 5 V therefore they cannot be directly connected to the Arduino Due (or any other 3.3 V MCU board). Also if more then one post-regulator modules wants to be connected to the single MCU board their SPI buses (X7 10-pin connector) must be isolated from each other even if used MCU board is capable of working with 5 V logic levels.

Digital to analog converter (DAC)

DAC device is used to provide the control voltage and current for the power supply. Using a SPI bus the user communicates to the DAC to program the new voltage at the DAC outputs (U_SET and I_SET). Also incorporated into the device is a power-on reset circuit which ensures that the DAC outputs power up at zero-scale and remain there until a valid write takes place.

The range of voltage the DAC can output is determined by the voltages at its reference pin (Vref) that is connected to the precision voltage reference of +2.5 V (IC7).

Important parameter that is used to determine DAC speed is settling time that represents the elapsed time from input code application until the output arrives at and remains within a specified error band around the final value. In our case it is max. 10 μs. Another factor is how complex and how much time require DAC channel programming. For this device it is accomplished by sending 24-bit stream (first byte represents command/register selection and remaining two 16-bit value that will be converted into analog voltage). SPI clock frequency used for transferring 24-bit value could go up to 30 MHz (!). Mentioned characteristics of the DAC provides enough margin to use it efficiently for the power supply programming where is typical that new output value is set in tens of milliseconds (that also include execution time of MCU code used for programming).

Analog to digital converter (ADC)

ADC is equipped with four channel input multiplexer and can accomplish up to 2 000 sampling per seconds. Its SPI clock is 4.096 MHz (4.5 MHz max). It is used to measure voltage and current control loops levels (U_MON, I_MON) but also DAC outputs (U_SET, I_SET). Selected ADC is 16-bit bipolar, but for our application only positive half of the full scale that represents only (unipolar) 15-bit. It also with internal 2.048 V voltage reference and many other interesting features that are not used in this project.

In contrast to DAC, the ADC requires bidirectional communication with the MCU. ADC’s output is used to transfer results of data acquisition at the end of each initiated measurement. For that purpose DOUT/DRDY output is used that is connected to MISO line. That output could be also used to notify SPI master (MCU) that data acquisition cycle on the selected input (one of four) is finished and that data are ready. Another possibility that is used in this design is deploying of dedicated DRDY output as a mean of notification. For more flexibility JP1 section is added which determine how DRDY will be used: directly by MCU or indirectly as state of the I/O expander’s bit 0. In the current firmware version the later method is used. Therefore JP1 require two jumpers on positions 1-2 and 3-4.

 

Fig. 7: Voltage reference, I/O expander, ADC and DAC

8-bit I/O expander

I/O expander is used to minimize number of required signal lines between post-regulator and MCU. In this way cable and connector’s pin numbers is reduced to 10 (that include 5 V and ground for supplying digital isolators) while total number of required digital isolator’s lines became 8 (6 input and 2 output lines). I/O lines are used in the following manner:

 

#

Direction

I/O name

Active

Desciption

0

Output

INT

Low

Generate MCU interrupt triggered by ADC DRDY or other I/O expander’s inputs

1

Output

SET_DP

Low

Enable or disable down programmer circuit

2

Input

CC_ACTIVE

High

CC (constant current) mode of operation is active

3

Input

TEMP_FREQ

High

Heatsink or transformer temperature presented as frequency.

4

Output

SET_100%

Low

If SMPS pre-regulator is used this signal controls so-called 100% duty cycle mode when switching mosfet is in continuous conducting mode. When active no high-frequency noise is presented that improve output ripply and noise figure (PARD).

5

Input

CV_ACTIVE

High

CV (constant voltage) mode of operation is active

6

Input

PWRGOOD

High

Power good input received from the pre-regulator module

7

Output

SET_OE

High

Enable or disable power output

Resolution

Some of the starting requirements for this project was resolution of 10 mV and 10 mA and output range of up to 50 V and up to 5 A. Mentioned requirements defines also resolution of digital devices required for programming and monitoring output voltage and current. For 50 V range we need at least 5 000 programming steps. Therefore DAC and ADC resolution has to be 13-bit or higher to provide 8 192 or more combinations (12-bit gives as only 4 096 possible combinations).

Quest for the proper DAC and ADC devices included interface selection, speed, availability (no exotic sources) and, of course the cost. Above mentioned devices used in the post-regulator provides decent price/performance for such kind of project and with 16-bit programming resolution and 15-bit measuring resolution theoretically the following precision could be achieved:

 

Range

16-bit programming

15-bit measurement

0 – 30 V

0.457 mV

0.916 mV

0 – 40 V

610 mV

1.22 mV

0 – 50 V

763 mV

1.53 mV

0 – 3.12 A

0.0476 mA

0.0952 mA

0 – 4.16 A

0.0636 mA

0.127 mA

0 – 5 A

0.0763 mA

0.153 mA

Optional manual control

Despite the fact that the power supply is intended to work with MCU for programming and monitoring, with few additional components it is possible to accomplish basic control manually. The manual control should simplify testing in the early stage when digital control such as Arduino shield is still not available.

Manual control of output voltage and current is possible using two additional multi-turn potentiometers (one for each function connected to the X3, as shown on Fig. 6) and one or two toggle switches for enabling power output (connected to the X4) and disabling down-programmer (X5).

Additionally it’s possible to connect LEDs for indication of the CV and CC mode (X6), OE (X4) and DP (X5) status.

PCB layout

PCB layout shown on Fig. 8 follows includes all mandatory and optional parts from schematics shown on Fig. 2, 6 and 7. Its design is influenced with some conclusions from discussion started here. Single ground plane is used under both analog and digital section that are located on two separate part of the board and special attention is taken to keep away digital from analog signals. Power mosfets Q1 and Q2 that are two only THT components are positioned on the same side on which the external heatsink has to be mounted. Power positive and negative lines are traced in close proximity with removed solder mask as it is shown on Fig. 9. That allows depositing of additional solder that makes power traces capable of carrying higher currents. Multiple vias that are used for power lines interconnection between top and bottom layer are also without solder mask for the same purpose. The PCB has 4 mounting holes on each corner with inner diameter of 3.2 mm for firm fixture.

 

Fig. 8: PCB layout (both sides, top, bottom)

 

Fig. 9: PCB bottom side (r4B43a)

SPICE model

Files:
LTspice EEZ PSU model 0.1 HOT

LTspice model of mosfet pre-regulator and post-regulator with CC and CV loops, OE and DP circuits. CC/CV indications are not added to decrease model complexity and improve simulation execution time.

License GNU GPLv3 Author This email address is being protected from spambots. You need JavaScript enabled to view it. Website Website Date 2016-01-11 Language  English File Size 170.91 KB Download 510 Download
TINA post-regulator model 0.1 HOT

TINA-TI model of mosfet post-regulator CV loop, OE and DP circuits.

License GNU GPLv3 Author This email address is being protected from spambots. You need JavaScript enabled to view it. Website Website Date 2016-01-11 Language  English File Size 8.71 KB Download 444 Download

Possible improvements and further development

  • DAC is currently connected to the same 5 V power supply that is used for the ADC and I/O expander. No separate analog and digital ground plane exists. According to the DAC8552 datasheet (pg. 20) its GND ideally would be connected directly to an analog ground plane that is separate from the ground connection for the digital components until they are connected at the power entry point (X2 in our case). Therefore some ground plane split could be introduced. As with the GND connection Vdd should be connected to a positive power-supply plane or trace that is separate from the connection for digital logic until they are connected at the power entry point.
  • Precise current measurement especially below 100 mA could make the power supply more useful when experimenting with low consumption circuits designed for battery operation. For that one or more current sense resistors could be introduced with selection that is based on the programmed max. current value. For resistor selection relays or mosfets could be used.
  • Currently post-regulator together with pre-regulator board have to be mounted with one side touching the read panel. That requires assembly of few cables that leads from connectors X1, X7 and optionally X8 to the Arduino Shield mounted on inner side of the front panel. Choosing another enclosure such as Galaxy Maggiorato 2U that has sides that can be used as a heatsink both pre- and post-regulator board could be mounted differently and rearranging of mentioned connectors would remove requirement for any extra cables. That requires also intervention on the Arduino shield board side but the end result will be simpler assembly and better usage of enclosure space so that for the same power rating a smaller enclosure can be used. The auxiliary power supply board in that case could be relocated somewhere on to the inner side of the rear panel.