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259 lines
10 KiB
259 lines
10 KiB
/** |
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****************************************************************************** |
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* @file n25q512a.h |
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* @author MCD Application Team |
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* @brief This file contains all the description of the N25Q512A QSPI memory. |
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****************************************************************************** |
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* @attention |
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* |
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* <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2> |
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* |
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* Redistribution and use in source and binary forms, with or without modification, |
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* are permitted provided that the following conditions are met: |
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* 1. Redistributions of source code must retain the above copyright notice, |
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* this list of conditions and the following disclaimer. |
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* 2. Redistributions in binary form must reproduce the above copyright notice, |
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* this list of conditions and the following disclaimer in the documentation |
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* and/or other materials provided with the distribution. |
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* 3. Neither the name of STMicroelectronics nor the names of its contributors |
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* may be used to endorse or promote products derived from this software |
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* without specific prior written permission. |
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* |
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
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* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
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* |
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****************************************************************************** |
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*/ |
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/* Define to prevent recursive inclusion -------------------------------------*/ |
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#ifndef __N25Q512A_H |
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#define __N25Q512A_H |
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#ifdef __cplusplus |
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extern "C" { |
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#endif |
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/* Includes ------------------------------------------------------------------*/ |
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/** @addtogroup BSP |
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* @{ |
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*/ |
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/** @addtogroup Components |
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* @{ |
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*/ |
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/** @addtogroup n25q512a |
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* @{ |
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*/ |
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/** @defgroup N25Q512A_Exported_Types |
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* @{ |
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*/ |
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/** |
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* @} |
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*/ |
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/** @defgroup N25Q512A_Exported_Constants |
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* @{ |
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*/ |
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/** |
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* @brief N25Q512A Configuration |
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*/ |
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#define N25Q512A_FLASH_SIZE 0x4000000 /* 512 MBits => 64MBytes */ |
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#define N25Q512A_SECTOR_SIZE 0x10000 /* 1024 sectors of 64KBytes */ |
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#define N25Q512A_SUBSECTOR_SIZE 0x1000 /* 16384 subsectors of 4kBytes */ |
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#define N25Q512A_PAGE_SIZE 0x100 /* 262144 pages of 256 bytes */ |
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#define N25Q512A_DUMMY_CYCLES_READ 8 |
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#define N25Q512A_DUMMY_CYCLES_READ_QUAD 10 |
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#define N25Q512A_DUMMY_CYCLES_READ_DTR 6 |
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#define N25Q512A_DUMMY_CYCLES_READ_QUAD_DTR 8 |
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#define N25Q512A_BULK_ERASE_MAX_TIME 480000 |
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#define N25Q512A_SECTOR_ERASE_MAX_TIME 3000 |
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#define N25Q512A_SUBSECTOR_ERASE_MAX_TIME 800 |
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/** |
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* @brief N25Q512A Commands |
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*/ |
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/* Reset Operations */ |
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#define RESET_ENABLE_CMD 0x66 |
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#define RESET_MEMORY_CMD 0x99 |
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/* Identification Operations */ |
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#define READ_ID_CMD 0x9E |
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#define READ_ID_CMD2 0x9F |
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#define MULTIPLE_IO_READ_ID_CMD 0xAF |
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#define READ_SERIAL_FLASH_DISCO_PARAM_CMD 0x5A |
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/* Read Operations */ |
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#define READ_CMD 0x03 |
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#define READ_4_BYTE_ADDR_CMD 0x13 |
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#define FAST_READ_CMD 0x0B |
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#define FAST_READ_DTR_CMD 0x0D |
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#define FAST_READ_4_BYTE_ADDR_CMD 0x0C |
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#define DUAL_OUT_FAST_READ_CMD 0x3B |
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#define DUAL_OUT_FAST_READ_DTR_CMD 0x3D |
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#define DUAL_OUT_FAST_READ_4_BYTE_ADDR_CMD 0x3C |
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#define DUAL_INOUT_FAST_READ_CMD 0xBB |
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#define DUAL_INOUT_FAST_READ_DTR_CMD 0xBD |
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#define DUAL_INOUT_FAST_READ_4_BYTE_ADDR_CMD 0xBC |
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#define QUAD_OUT_FAST_READ_CMD 0x6B |
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#define QUAD_OUT_FAST_READ_DTR_CMD 0x6D |
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#define QUAD_OUT_FAST_READ_4_BYTE_ADDR_CMD 0x6C |
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#define QUAD_INOUT_FAST_READ_CMD 0xEB |
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#define QUAD_INOUT_FAST_READ_DTR_CMD 0xED |
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#define QUAD_INOUT_FAST_READ_4_BYTE_ADDR_CMD 0xEC |
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/* Write Operations */ |
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#define WRITE_ENABLE_CMD 0x06 |
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#define WRITE_DISABLE_CMD 0x04 |
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/* Register Operations */ |
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#define READ_STATUS_REG_CMD 0x05 |
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#define WRITE_STATUS_REG_CMD 0x01 |
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#define READ_LOCK_REG_CMD 0xE8 |
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#define WRITE_LOCK_REG_CMD 0xE5 |
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#define READ_FLAG_STATUS_REG_CMD 0x70 |
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#define CLEAR_FLAG_STATUS_REG_CMD 0x50 |
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#define READ_NONVOL_CFG_REG_CMD 0xB5 |
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#define WRITE_NONVOL_CFG_REG_CMD 0xB1 |
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#define READ_VOL_CFG_REG_CMD 0x85 |
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#define WRITE_VOL_CFG_REG_CMD 0x81 |
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#define READ_ENHANCED_VOL_CFG_REG_CMD 0x65 |
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#define WRITE_ENHANCED_VOL_CFG_REG_CMD 0x61 |
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#define READ_EXT_ADDR_REG_CMD 0xC8 |
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#define WRITE_EXT_ADDR_REG_CMD 0xC5 |
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/* Program Operations */ |
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#define PAGE_PROG_CMD 0x02 |
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#define PAGE_PROG_4_BYTE_ADDR_CMD 0x12 |
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#define DUAL_IN_FAST_PROG_CMD 0xA2 |
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#define EXT_DUAL_IN_FAST_PROG_CMD 0xD2 |
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#define QUAD_IN_FAST_PROG_CMD 0x32 |
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#define EXT_QUAD_IN_FAST_PROG_CMD 0x12 /*0x38*/ |
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#define QUAD_IN_FAST_PROG_4_BYTE_ADDR_CMD 0x34 |
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/* Erase Operations */ |
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#define SUBSECTOR_ERASE_CMD 0x20 |
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#define SUBSECTOR_ERASE_4_BYTE_ADDR_CMD 0x21 |
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#define SECTOR_ERASE_CMD 0xD8 |
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#define SECTOR_ERASE_4_BYTE_ADDR_CMD 0xDC |
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#define BULK_ERASE_CMD 0xC7 |
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#define PROG_ERASE_RESUME_CMD 0x7A |
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#define PROG_ERASE_SUSPEND_CMD 0x75 |
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/* One-Time Programmable Operations */ |
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#define READ_OTP_ARRAY_CMD 0x4B |
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#define PROG_OTP_ARRAY_CMD 0x42 |
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/* 4-byte Address Mode Operations */ |
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#define ENTER_4_BYTE_ADDR_MODE_CMD 0xB7 |
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#define EXIT_4_BYTE_ADDR_MODE_CMD 0xE9 |
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/* Quad Operations */ |
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#define ENTER_QUAD_CMD 0x35 |
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#define EXIT_QUAD_CMD 0xF5 |
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/** |
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* @brief N25Q512A Registers |
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*/ |
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/* Status Register */ |
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#define N25Q512A_SR_WIP ((uint8_t)0x01) /*!< Write in progress */ |
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#define N25Q512A_SR_WREN ((uint8_t)0x02) /*!< Write enable latch */ |
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#define N25Q512A_SR_BLOCKPR ((uint8_t)0x5C) /*!< Block protected against program and erase operations */ |
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#define N25Q512A_SR_PRBOTTOM ((uint8_t)0x20) /*!< Protected memory area defined by BLOCKPR starts from top or bottom */ |
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#define N25Q512A_SR_SRWREN ((uint8_t)0x80) /*!< Status register write enable/disable */ |
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/* Non volatile Configuration Register */ |
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#define N25Q512A_NVCR_NBADDR ((uint16_t)0x0001) /*!< 3-bytes or 4-bytes addressing */ |
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#define N25Q512A_NVCR_SEGMENT ((uint16_t)0x0002) /*!< Upper or lower 128Mb segment selected by default */ |
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#define N25Q512A_NVCR_DUAL ((uint16_t)0x0004) /*!< Dual I/O protocol */ |
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#define N25Q512A_NVCR_QUAB ((uint16_t)0x0008) /*!< Quad I/O protocol */ |
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#define N25Q512A_NVCR_RH ((uint16_t)0x0010) /*!< Reset/hold */ |
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#define N25Q512A_NVCR_ODS ((uint16_t)0x01C0) /*!< Output driver strength */ |
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#define N25Q512A_NVCR_XIP ((uint16_t)0x0E00) /*!< XIP mode at power-on reset */ |
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#define N25Q512A_NVCR_NB_DUMMY ((uint16_t)0xF000) /*!< Number of dummy clock cycles */ |
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/* Volatile Configuration Register */ |
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#define N25Q512A_VCR_WRAP ((uint8_t)0x03) /*!< Wrap */ |
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#define N25Q512A_VCR_XIP ((uint8_t)0x08) /*!< XIP */ |
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#define N25Q512A_VCR_NB_DUMMY ((uint8_t)0xF0) /*!< Number of dummy clock cycles */ |
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/* Extended Address Register */ |
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#define N25Q512A_EAR_A24 ((uint8_t)0x01) /*!< Select the lower or upper 128Mb segment */ |
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/* Enhanced Volatile Configuration Register */ |
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#define N25Q512A_EVCR_ODS ((uint8_t)0x07) /*!< Output driver strength */ |
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#define N25Q512A_EVCR_VPPA ((uint8_t)0x08) /*!< Vpp accelerator */ |
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#define N25Q512A_EVCR_RH ((uint8_t)0x10) /*!< Reset/hold */ |
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#define N25Q512A_EVCR_DUAL ((uint8_t)0x40) /*!< Dual I/O protocol */ |
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#define N25Q512A_EVCR_QUAD ((uint8_t)0x80) /*!< Quad I/O protocol */ |
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/* Flag Status Register */ |
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#define N25Q512A_FSR_NBADDR ((uint8_t)0x01) /*!< 3-bytes or 4-bytes addressing */ |
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#define N25Q512A_FSR_PRERR ((uint8_t)0x02) /*!< Protection error */ |
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#define N25Q512A_FSR_PGSUS ((uint8_t)0x04) /*!< Program operation suspended */ |
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#define N25Q512A_FSR_VPPERR ((uint8_t)0x08) /*!< Invalid voltage during program or erase */ |
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#define N25Q512A_FSR_PGERR ((uint8_t)0x10) /*!< Program error */ |
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#define N25Q512A_FSR_ERERR ((uint8_t)0x20) /*!< Erase error */ |
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#define N25Q512A_FSR_ERSUS ((uint8_t)0x40) /*!< Erase operation suspended */ |
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#define N25Q512A_FSR_READY ((uint8_t)0x80) /*!< Ready or command in progress */ |
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/** |
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* @} |
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*/ |
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/** @defgroup N25Q512A_Exported_Functions |
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* @{ |
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*/ |
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/** |
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* @} |
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*/ |
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#ifdef __cplusplus |
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} |
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#endif |
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#endif /* __N25Q512A_H */ |
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/** |
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* @} |
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*/ |
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/** |
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* @} |
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*/ |
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/** |
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* @} |
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*/ |
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/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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