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3524 lines
229 KiB
3524 lines
229 KiB
/** |
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****************************************************************************** |
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* @file stm32f7xx_hal_rcc_ex.h |
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* @author MCD Application Team |
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* @brief Header file of RCC HAL Extension module. |
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****************************************************************************** |
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* @attention |
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* |
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* <h2><center>© Copyright (c) 2017 STMicroelectronics. |
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* All rights reserved.</center></h2> |
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* |
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* This software component is licensed by ST under BSD 3-Clause license, |
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* the "License"; You may not use this file except in compliance with the |
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* License. You may obtain a copy of the License at: |
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* opensource.org/licenses/BSD-3-Clause |
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* |
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****************************************************************************** |
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*/ |
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/* Define to prevent recursive inclusion -------------------------------------*/ |
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#ifndef __STM32F7xx_HAL_RCC_EX_H |
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#define __STM32F7xx_HAL_RCC_EX_H |
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#ifdef __cplusplus |
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extern "C" { |
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#endif |
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/* Includes ------------------------------------------------------------------*/ |
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#include "stm32f7xx_hal_def.h" |
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/** @addtogroup STM32F7xx_HAL_Driver |
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* @{ |
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*/ |
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/** @addtogroup RCCEx |
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* @{ |
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*/ |
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/* Exported types ------------------------------------------------------------*/ |
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/** @defgroup RCCEx_Exported_Types RCCEx Exported Types |
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* @{ |
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*/ |
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/** |
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* @brief RCC PLL configuration structure definition |
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*/ |
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typedef struct |
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{ |
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uint32_t PLLState; /*!< The new state of the PLL. |
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This parameter can be a value of @ref RCC_PLL_Config */ |
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uint32_t PLLSource; /*!< RCC_PLLSource: PLL entry clock source. |
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This parameter must be a value of @ref RCC_PLL_Clock_Source */ |
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uint32_t PLLM; /*!< PLLM: Division factor for PLL VCO input clock. |
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This parameter must be a number between Min_Data = 2 and Max_Data = 63 */ |
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uint32_t PLLN; /*!< PLLN: Multiplication factor for PLL VCO output clock. |
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This parameter must be a number between Min_Data = 50 and Max_Data = 432 */ |
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uint32_t PLLP; /*!< PLLP: Division factor for main system clock (SYSCLK). |
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This parameter must be a value of @ref RCC_PLLP_Clock_Divider */ |
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uint32_t PLLQ; /*!< PLLQ: Division factor for OTG FS, SDMMC and RNG clocks. |
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This parameter must be a number between Min_Data = 2 and Max_Data = 15 */ |
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#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) |
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uint32_t PLLR; /*!< PLLR: Division factor for DSI clock. |
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This parameter must be a number between Min_Data = 2 and Max_Data = 7 */ |
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#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ |
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}RCC_PLLInitTypeDef; |
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/** |
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* @brief PLLI2S Clock structure definition |
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*/ |
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typedef struct |
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{ |
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uint32_t PLLI2SN; /*!< Specifies the multiplication factor for PLLI2S VCO output clock. |
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This parameter must be a number between Min_Data = 50 and Max_Data = 432. |
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This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */ |
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uint32_t PLLI2SR; /*!< Specifies the division factor for I2S clock. |
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This parameter must be a number between Min_Data = 2 and Max_Data = 7. |
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This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */ |
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uint32_t PLLI2SQ; /*!< Specifies the division factor for SAI1 clock. |
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This parameter must be a number between Min_Data = 2 and Max_Data = 15. |
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This parameter will be used only when PLLI2S is selected as Clock Source SAI */ |
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#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) || defined (STM32F767xx) || \ |
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defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx) |
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uint32_t PLLI2SP; /*!< Specifies the division factor for SPDIF-RX clock. |
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This parameter must be a value of @ref RCCEx_PLLI2SP_Clock_Divider. |
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This parameter will be used only when PLLI2S is selected as Clock Source SPDIF-RX */ |
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#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ |
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}RCC_PLLI2SInitTypeDef; |
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/** |
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* @brief PLLSAI Clock structure definition |
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*/ |
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typedef struct |
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{ |
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uint32_t PLLSAIN; /*!< Specifies the multiplication factor for PLLI2S VCO output clock. |
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This parameter must be a number between Min_Data = 50 and Max_Data = 432. |
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This parameter will be used only when PLLSAI is selected as Clock Source SAI or LTDC */ |
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uint32_t PLLSAIQ; /*!< Specifies the division factor for SAI1 clock. |
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This parameter must be a number between Min_Data = 2 and Max_Data = 15. |
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This parameter will be used only when PLLSAI is selected as Clock Source SAI or LTDC */ |
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#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) || defined (STM32F767xx) || \ |
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defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx) |
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uint32_t PLLSAIR; /*!< specifies the division factor for LTDC clock |
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This parameter must be a number between Min_Data = 2 and Max_Data = 7. |
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This parameter will be used only when PLLSAI is selected as Clock Source LTDC */ |
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#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ |
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uint32_t PLLSAIP; /*!< Specifies the division factor for 48MHz clock. |
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This parameter must be a value of @ref RCCEx_PLLSAIP_Clock_Divider |
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This parameter will be used only when PLLSAI is disabled */ |
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}RCC_PLLSAIInitTypeDef; |
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/** |
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* @brief RCC extended clocks structure definition |
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*/ |
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typedef struct |
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{ |
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uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured. |
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This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */ |
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RCC_PLLI2SInitTypeDef PLLI2S; /*!< PLL I2S structure parameters. |
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This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */ |
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RCC_PLLSAIInitTypeDef PLLSAI; /*!< PLL SAI structure parameters. |
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This parameter will be used only when PLLI2S is selected as Clock Source SAI or LTDC */ |
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uint32_t PLLI2SDivQ; /*!< Specifies the PLLI2S division factor for SAI1 clock. |
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This parameter must be a number between Min_Data = 1 and Max_Data = 32 |
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This parameter will be used only when PLLI2S is selected as Clock Source SAI */ |
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uint32_t PLLSAIDivQ; /*!< Specifies the PLLI2S division factor for SAI1 clock. |
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This parameter must be a number between Min_Data = 1 and Max_Data = 32 |
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This parameter will be used only when PLLSAI is selected as Clock Source SAI */ |
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uint32_t PLLSAIDivR; /*!< Specifies the PLLSAI division factor for LTDC clock. |
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This parameter must be one value of @ref RCCEx_PLLSAI_DIVR */ |
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uint32_t RTCClockSelection; /*!< Specifies RTC Clock source Selection. |
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This parameter can be a value of @ref RCC_RTC_Clock_Source */ |
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uint32_t I2sClockSelection; /*!< Specifies I2S Clock source Selection. |
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This parameter can be a value of @ref RCCEx_I2S_Clock_Source */ |
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uint32_t TIMPresSelection; /*!< Specifies TIM Clock Prescalers Selection. |
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This parameter can be a value of @ref RCCEx_TIM_Prescaler_Selection */ |
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uint32_t Sai1ClockSelection; /*!< Specifies SAI1 Clock Prescalers Selection |
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This parameter can be a value of @ref RCCEx_SAI1_Clock_Source */ |
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uint32_t Sai2ClockSelection; /*!< Specifies SAI2 Clock Prescalers Selection |
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This parameter can be a value of @ref RCCEx_SAI2_Clock_Source */ |
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uint32_t Usart1ClockSelection; /*!< USART1 clock source |
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This parameter can be a value of @ref RCCEx_USART1_Clock_Source */ |
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uint32_t Usart2ClockSelection; /*!< USART2 clock source |
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This parameter can be a value of @ref RCCEx_USART2_Clock_Source */ |
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uint32_t Usart3ClockSelection; /*!< USART3 clock source |
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This parameter can be a value of @ref RCCEx_USART3_Clock_Source */ |
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uint32_t Uart4ClockSelection; /*!< UART4 clock source |
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This parameter can be a value of @ref RCCEx_UART4_Clock_Source */ |
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uint32_t Uart5ClockSelection; /*!< UART5 clock source |
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This parameter can be a value of @ref RCCEx_UART5_Clock_Source */ |
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uint32_t Usart6ClockSelection; /*!< USART6 clock source |
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This parameter can be a value of @ref RCCEx_USART6_Clock_Source */ |
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uint32_t Uart7ClockSelection; /*!< UART7 clock source |
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This parameter can be a value of @ref RCCEx_UART7_Clock_Source */ |
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uint32_t Uart8ClockSelection; /*!< UART8 clock source |
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This parameter can be a value of @ref RCCEx_UART8_Clock_Source */ |
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uint32_t I2c1ClockSelection; /*!< I2C1 clock source |
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This parameter can be a value of @ref RCCEx_I2C1_Clock_Source */ |
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uint32_t I2c2ClockSelection; /*!< I2C2 clock source |
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This parameter can be a value of @ref RCCEx_I2C2_Clock_Source */ |
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uint32_t I2c3ClockSelection; /*!< I2C3 clock source |
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This parameter can be a value of @ref RCCEx_I2C3_Clock_Source */ |
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uint32_t I2c4ClockSelection; /*!< I2C4 clock source |
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This parameter can be a value of @ref RCCEx_I2C4_Clock_Source */ |
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uint32_t Lptim1ClockSelection; /*!< Specifies LPTIM1 clock source |
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This parameter can be a value of @ref RCCEx_LPTIM1_Clock_Source */ |
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uint32_t CecClockSelection; /*!< CEC clock source |
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This parameter can be a value of @ref RCCEx_CEC_Clock_Source */ |
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uint32_t Clk48ClockSelection; /*!< Specifies 48Mhz clock source used by USB OTG FS, RNG and SDMMC |
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This parameter can be a value of @ref RCCEx_CLK48_Clock_Source */ |
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uint32_t Sdmmc1ClockSelection; /*!< SDMMC1 clock source |
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This parameter can be a value of @ref RCCEx_SDMMC1_Clock_Source */ |
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#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F765xx) ||\ |
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defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F730xx) |
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uint32_t Sdmmc2ClockSelection; /*!< SDMMC2 clock source |
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This parameter can be a value of @ref RCCEx_SDMMC2_Clock_Source */ |
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#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F730xx */ |
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#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) |
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uint32_t Dfsdm1ClockSelection; /*!< DFSDM1 clock source |
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This parameter can be a value of @ref RCCEx_DFSDM1_Kernel_Clock_Source */ |
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uint32_t Dfsdm1AudioClockSelection; /*!< DFSDM1 clock source |
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This parameter can be a value of @ref RCCEx_DFSDM1_AUDIO_Clock_Source */ |
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#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ |
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}RCC_PeriphCLKInitTypeDef; |
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/** |
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* @} |
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*/ |
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/* Exported constants --------------------------------------------------------*/ |
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/** @defgroup RCCEx_Exported_Constants RCCEx Exported Constants |
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* @{ |
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*/ |
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/** @defgroup RCCEx_Periph_Clock_Selection RCC Periph Clock Selection |
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* @{ |
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*/ |
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#define RCC_PERIPHCLK_I2S ((uint32_t)0x00000001U) |
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#if defined(STM32F746xx) || defined(STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx) |
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#define RCC_PERIPHCLK_LTDC ((uint32_t)0x00000008U) |
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#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ |
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#define RCC_PERIPHCLK_TIM ((uint32_t)0x00000010U) |
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#define RCC_PERIPHCLK_RTC ((uint32_t)0x00000020U) |
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#define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000040U) |
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#define RCC_PERIPHCLK_USART2 ((uint32_t)0x00000080U) |
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#define RCC_PERIPHCLK_USART3 ((uint32_t)0x00000100U) |
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#define RCC_PERIPHCLK_UART4 ((uint32_t)0x00000200U) |
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#define RCC_PERIPHCLK_UART5 ((uint32_t)0x00000400U) |
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#define RCC_PERIPHCLK_USART6 ((uint32_t)0x00000800U) |
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#define RCC_PERIPHCLK_UART7 ((uint32_t)0x00001000U) |
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#define RCC_PERIPHCLK_UART8 ((uint32_t)0x00002000U) |
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#define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00004000U) |
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#define RCC_PERIPHCLK_I2C2 ((uint32_t)0x00008000U) |
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#define RCC_PERIPHCLK_I2C3 ((uint32_t)0x00010000U) |
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#define RCC_PERIPHCLK_I2C4 ((uint32_t)0x00020000U) |
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#define RCC_PERIPHCLK_LPTIM1 ((uint32_t)0x00040000U) |
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#define RCC_PERIPHCLK_SAI1 ((uint32_t)0x00080000U) |
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#define RCC_PERIPHCLK_SAI2 ((uint32_t)0x00100000U) |
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#define RCC_PERIPHCLK_CLK48 ((uint32_t)0x00200000U) |
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#define RCC_PERIPHCLK_CEC ((uint32_t)0x00400000U) |
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#define RCC_PERIPHCLK_SDMMC1 ((uint32_t)0x00800000U) |
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#define RCC_PERIPHCLK_SPDIFRX ((uint32_t)0x01000000U) |
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#define RCC_PERIPHCLK_PLLI2S ((uint32_t)0x02000000U) |
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#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F765xx) ||\ |
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defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F730xx) |
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#define RCC_PERIPHCLK_SDMMC2 ((uint32_t)0x04000000U) |
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#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F730xx */ |
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#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) |
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#define RCC_PERIPHCLK_DFSDM1 ((uint32_t)0x08000000U) |
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#define RCC_PERIPHCLK_DFSDM1_AUDIO ((uint32_t)0x10000000U) |
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#endif /* STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ |
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/** |
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* @} |
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*/ |
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#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) || defined (STM32F767xx) || \ |
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defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx) |
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/** @defgroup RCCEx_PLLI2SP_Clock_Divider RCCEx PLLI2SP Clock Divider |
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* @{ |
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*/ |
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#define RCC_PLLI2SP_DIV2 ((uint32_t)0x00000000U) |
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#define RCC_PLLI2SP_DIV4 ((uint32_t)0x00000001U) |
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#define RCC_PLLI2SP_DIV6 ((uint32_t)0x00000002U) |
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#define RCC_PLLI2SP_DIV8 ((uint32_t)0x00000003U) |
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/** |
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* @} |
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*/ |
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#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ |
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/** @defgroup RCCEx_PLLSAIP_Clock_Divider RCCEx PLLSAIP Clock Divider |
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* @{ |
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*/ |
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#define RCC_PLLSAIP_DIV2 ((uint32_t)0x00000000U) |
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#define RCC_PLLSAIP_DIV4 ((uint32_t)0x00000001U) |
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#define RCC_PLLSAIP_DIV6 ((uint32_t)0x00000002U) |
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#define RCC_PLLSAIP_DIV8 ((uint32_t)0x00000003U) |
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/** |
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* @} |
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*/ |
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/** @defgroup RCCEx_PLLSAI_DIVR RCCEx PLLSAI DIVR |
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* @{ |
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*/ |
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#define RCC_PLLSAIDIVR_2 ((uint32_t)0x00000000U) |
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#define RCC_PLLSAIDIVR_4 RCC_DCKCFGR1_PLLSAIDIVR_0 |
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#define RCC_PLLSAIDIVR_8 RCC_DCKCFGR1_PLLSAIDIVR_1 |
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#define RCC_PLLSAIDIVR_16 RCC_DCKCFGR1_PLLSAIDIVR |
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/** |
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* @} |
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*/ |
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/** @defgroup RCCEx_I2S_Clock_Source RCCEx I2S Clock Source |
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* @{ |
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*/ |
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#define RCC_I2SCLKSOURCE_PLLI2S ((uint32_t)0x00000000U) |
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#define RCC_I2SCLKSOURCE_EXT RCC_CFGR_I2SSRC |
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/** |
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* @} |
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*/ |
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/** @defgroup RCCEx_SAI1_Clock_Source RCCEx SAI1 Clock Source |
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* @{ |
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*/ |
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#define RCC_SAI1CLKSOURCE_PLLSAI ((uint32_t)0x00000000U) |
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#define RCC_SAI1CLKSOURCE_PLLI2S RCC_DCKCFGR1_SAI1SEL_0 |
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#define RCC_SAI1CLKSOURCE_PIN RCC_DCKCFGR1_SAI1SEL_1 |
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#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) |
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#define RCC_SAI1CLKSOURCE_PLLSRC RCC_DCKCFGR1_SAI1SEL |
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#endif /* STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ |
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/** |
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* @} |
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*/ |
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/** @defgroup RCCEx_SAI2_Clock_Source RCCEx SAI2 Clock Source |
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* @{ |
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*/ |
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#define RCC_SAI2CLKSOURCE_PLLSAI ((uint32_t)0x00000000U) |
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#define RCC_SAI2CLKSOURCE_PLLI2S RCC_DCKCFGR1_SAI2SEL_0 |
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#define RCC_SAI2CLKSOURCE_PIN RCC_DCKCFGR1_SAI2SEL_1 |
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#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) |
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#define RCC_SAI2CLKSOURCE_PLLSRC RCC_DCKCFGR1_SAI2SEL |
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#endif /* STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ |
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/** |
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* @} |
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*/ |
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/** @defgroup RCCEx_CEC_Clock_Source RCCEx CEC Clock Source |
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* @{ |
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*/ |
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#define RCC_CECCLKSOURCE_LSE ((uint32_t)0x00000000U) |
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#define RCC_CECCLKSOURCE_HSI RCC_DCKCFGR2_CECSEL /* CEC clock is HSI/488*/ |
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/** |
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* @} |
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*/ |
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/** @defgroup RCCEx_USART1_Clock_Source RCCEx USART1 Clock Source |
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* @{ |
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*/ |
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#define RCC_USART1CLKSOURCE_PCLK2 ((uint32_t)0x00000000U) |
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#define RCC_USART1CLKSOURCE_SYSCLK RCC_DCKCFGR2_USART1SEL_0 |
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#define RCC_USART1CLKSOURCE_HSI RCC_DCKCFGR2_USART1SEL_1 |
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#define RCC_USART1CLKSOURCE_LSE RCC_DCKCFGR2_USART1SEL |
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/** |
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* @} |
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*/ |
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/** @defgroup RCCEx_USART2_Clock_Source RCCEx USART2 Clock Source |
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* @{ |
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*/ |
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#define RCC_USART2CLKSOURCE_PCLK1 ((uint32_t)0x00000000U) |
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#define RCC_USART2CLKSOURCE_SYSCLK RCC_DCKCFGR2_USART2SEL_0 |
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#define RCC_USART2CLKSOURCE_HSI RCC_DCKCFGR2_USART2SEL_1 |
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#define RCC_USART2CLKSOURCE_LSE RCC_DCKCFGR2_USART2SEL |
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/** |
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* @} |
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*/ |
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/** @defgroup RCCEx_USART3_Clock_Source RCCEx USART3 Clock Source |
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* @{ |
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*/ |
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#define RCC_USART3CLKSOURCE_PCLK1 ((uint32_t)0x00000000U) |
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#define RCC_USART3CLKSOURCE_SYSCLK RCC_DCKCFGR2_USART3SEL_0 |
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#define RCC_USART3CLKSOURCE_HSI RCC_DCKCFGR2_USART3SEL_1 |
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#define RCC_USART3CLKSOURCE_LSE RCC_DCKCFGR2_USART3SEL |
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/** |
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* @} |
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*/ |
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/** @defgroup RCCEx_UART4_Clock_Source RCCEx UART4 Clock Source |
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* @{ |
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*/ |
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#define RCC_UART4CLKSOURCE_PCLK1 ((uint32_t)0x00000000U) |
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#define RCC_UART4CLKSOURCE_SYSCLK RCC_DCKCFGR2_UART4SEL_0 |
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#define RCC_UART4CLKSOURCE_HSI RCC_DCKCFGR2_UART4SEL_1 |
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#define RCC_UART4CLKSOURCE_LSE RCC_DCKCFGR2_UART4SEL |
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/** |
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* @} |
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*/ |
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/** @defgroup RCCEx_UART5_Clock_Source RCCEx UART5 Clock Source |
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* @{ |
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*/ |
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#define RCC_UART5CLKSOURCE_PCLK1 ((uint32_t)0x00000000U) |
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#define RCC_UART5CLKSOURCE_SYSCLK RCC_DCKCFGR2_UART5SEL_0 |
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#define RCC_UART5CLKSOURCE_HSI RCC_DCKCFGR2_UART5SEL_1 |
|
#define RCC_UART5CLKSOURCE_LSE RCC_DCKCFGR2_UART5SEL |
|
/** |
|
* @} |
|
*/ |
|
|
|
/** @defgroup RCCEx_USART6_Clock_Source RCCEx USART6 Clock Source |
|
* @{ |
|
*/ |
|
#define RCC_USART6CLKSOURCE_PCLK2 ((uint32_t)0x00000000U) |
|
#define RCC_USART6CLKSOURCE_SYSCLK RCC_DCKCFGR2_USART6SEL_0 |
|
#define RCC_USART6CLKSOURCE_HSI RCC_DCKCFGR2_USART6SEL_1 |
|
#define RCC_USART6CLKSOURCE_LSE RCC_DCKCFGR2_USART6SEL |
|
/** |
|
* @} |
|
*/ |
|
|
|
/** @defgroup RCCEx_UART7_Clock_Source RCCEx UART7 Clock Source |
|
* @{ |
|
*/ |
|
#define RCC_UART7CLKSOURCE_PCLK1 ((uint32_t)0x00000000U) |
|
#define RCC_UART7CLKSOURCE_SYSCLK RCC_DCKCFGR2_UART7SEL_0 |
|
#define RCC_UART7CLKSOURCE_HSI RCC_DCKCFGR2_UART7SEL_1 |
|
#define RCC_UART7CLKSOURCE_LSE RCC_DCKCFGR2_UART7SEL |
|
/** |
|
* @} |
|
*/ |
|
|
|
/** @defgroup RCCEx_UART8_Clock_Source RCCEx UART8 Clock Source |
|
* @{ |
|
*/ |
|
#define RCC_UART8CLKSOURCE_PCLK1 ((uint32_t)0x00000000U) |
|
#define RCC_UART8CLKSOURCE_SYSCLK RCC_DCKCFGR2_UART8SEL_0 |
|
#define RCC_UART8CLKSOURCE_HSI RCC_DCKCFGR2_UART8SEL_1 |
|
#define RCC_UART8CLKSOURCE_LSE RCC_DCKCFGR2_UART8SEL |
|
/** |
|
* @} |
|
*/ |
|
|
|
/** @defgroup RCCEx_I2C1_Clock_Source RCCEx I2C1 Clock Source |
|
* @{ |
|
*/ |
|
#define RCC_I2C1CLKSOURCE_PCLK1 ((uint32_t)0x00000000U) |
|
#define RCC_I2C1CLKSOURCE_SYSCLK RCC_DCKCFGR2_I2C1SEL_0 |
|
#define RCC_I2C1CLKSOURCE_HSI RCC_DCKCFGR2_I2C1SEL_1 |
|
/** |
|
* @} |
|
*/ |
|
|
|
/** @defgroup RCCEx_I2C2_Clock_Source RCCEx I2C2 Clock Source |
|
* @{ |
|
*/ |
|
#define RCC_I2C2CLKSOURCE_PCLK1 ((uint32_t)0x00000000U) |
|
#define RCC_I2C2CLKSOURCE_SYSCLK RCC_DCKCFGR2_I2C2SEL_0 |
|
#define RCC_I2C2CLKSOURCE_HSI RCC_DCKCFGR2_I2C2SEL_1 |
|
|
|
/** |
|
* @} |
|
*/ |
|
|
|
/** @defgroup RCCEx_I2C3_Clock_Source RCCEx I2C3 Clock Source |
|
* @{ |
|
*/ |
|
#define RCC_I2C3CLKSOURCE_PCLK1 ((uint32_t)0x00000000U) |
|
#define RCC_I2C3CLKSOURCE_SYSCLK RCC_DCKCFGR2_I2C3SEL_0 |
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#define RCC_I2C3CLKSOURCE_HSI RCC_DCKCFGR2_I2C3SEL_1 |
|
/** |
|
* @} |
|
*/ |
|
|
|
/** @defgroup RCCEx_I2C4_Clock_Source RCCEx I2C4 Clock Source |
|
* @{ |
|
*/ |
|
#define RCC_I2C4CLKSOURCE_PCLK1 ((uint32_t)0x00000000U) |
|
#define RCC_I2C4CLKSOURCE_SYSCLK RCC_DCKCFGR2_I2C4SEL_0 |
|
#define RCC_I2C4CLKSOURCE_HSI RCC_DCKCFGR2_I2C4SEL_1 |
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/** |
|
* @} |
|
*/ |
|
|
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/** @defgroup RCCEx_LPTIM1_Clock_Source RCCEx LPTIM1 Clock Source |
|
* @{ |
|
*/ |
|
#define RCC_LPTIM1CLKSOURCE_PCLK1 ((uint32_t)0x00000000U) |
|
#define RCC_LPTIM1CLKSOURCE_LSI RCC_DCKCFGR2_LPTIM1SEL_0 |
|
#define RCC_LPTIM1CLKSOURCE_HSI RCC_DCKCFGR2_LPTIM1SEL_1 |
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#define RCC_LPTIM1CLKSOURCE_LSE RCC_DCKCFGR2_LPTIM1SEL |
|
|
|
/** |
|
* @} |
|
*/ |
|
|
|
/** @defgroup RCCEx_CLK48_Clock_Source RCCEx CLK48 Clock Source |
|
* @{ |
|
*/ |
|
#define RCC_CLK48SOURCE_PLL ((uint32_t)0x00000000U) |
|
#define RCC_CLK48SOURCE_PLLSAIP RCC_DCKCFGR2_CK48MSEL |
|
/** |
|
* @} |
|
*/ |
|
|
|
/** @defgroup RCCEx_TIM_Prescaler_Selection RCCEx TIM Prescaler Selection |
|
* @{ |
|
*/ |
|
#define RCC_TIMPRES_DESACTIVATED ((uint32_t)0x00000000U) |
|
#define RCC_TIMPRES_ACTIVATED RCC_DCKCFGR1_TIMPRE |
|
/** |
|
* @} |
|
*/ |
|
|
|
/** @defgroup RCCEx_SDMMC1_Clock_Source RCCEx SDMMC1 Clock Source |
|
* @{ |
|
*/ |
|
#define RCC_SDMMC1CLKSOURCE_CLK48 ((uint32_t)0x00000000U) |
|
#define RCC_SDMMC1CLKSOURCE_SYSCLK RCC_DCKCFGR2_SDMMC1SEL |
|
/** |
|
* @} |
|
*/ |
|
|
|
#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F765xx) ||\ |
|
defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F730xx) |
|
/** @defgroup RCCEx_SDMMC2_Clock_Source RCCEx SDMMC2 Clock Source |
|
* @{ |
|
*/ |
|
#define RCC_SDMMC2CLKSOURCE_CLK48 ((uint32_t)0x00000000U) |
|
#define RCC_SDMMC2CLKSOURCE_SYSCLK RCC_DCKCFGR2_SDMMC2SEL |
|
/** |
|
* @} |
|
*/ |
|
#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F730xx */ |
|
|
|
#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) |
|
/** @defgroup RCCEx_DFSDM1_Kernel_Clock_Source RCCEx DFSDM1 Kernel Clock Source |
|
* @{ |
|
*/ |
|
#define RCC_DFSDM1CLKSOURCE_PCLK2 ((uint32_t)0x00000000U) |
|
#define RCC_DFSDM1CLKSOURCE_SYSCLK RCC_DCKCFGR1_DFSDM1SEL |
|
/** |
|
* @} |
|
*/ |
|
|
|
/** @defgroup RCCEx_DFSDM1_AUDIO_Clock_Source RCCEx DFSDM1 AUDIO Clock Source |
|
* @{ |
|
*/ |
|
#define RCC_DFSDM1AUDIOCLKSOURCE_SAI1 ((uint32_t)0x00000000U) |
|
#define RCC_DFSDM1AUDIOCLKSOURCE_SAI2 RCC_DCKCFGR1_ADFSDM1SEL |
|
/** |
|
* @} |
|
*/ |
|
#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ |
|
|
|
#if defined (STM32F769xx) || defined (STM32F779xx) |
|
/** @defgroup RCCEx_DSI_Clock_Source RCC DSI Clock Source |
|
* @{ |
|
*/ |
|
#define RCC_DSICLKSOURCE_DSIPHY ((uint32_t)0x00000000U) |
|
#define RCC_DSICLKSOURCE_PLLR ((uint32_t)RCC_DCKCFGR2_DSISEL) |
|
/** |
|
* @} |
|
*/ |
|
#endif /* STM32F769xx || STM32F779xx */ |
|
|
|
/** |
|
* @} |
|
*/ |
|
|
|
/* Exported macro ------------------------------------------------------------*/ |
|
/** @defgroup RCCEx_Exported_Macros RCCEx Exported Macros |
|
* @{ |
|
*/ |
|
/** @defgroup RCCEx_Peripheral_Clock_Enable_Disable RCCEx_Peripheral_Clock_Enable_Disable |
|
* @brief Enables or disables the AHB/APB peripheral clock. |
|
* @note After reset, the peripheral clock (used for registers read/write access) |
|
* is disabled and the application software has to enable this clock before |
|
* using it. |
|
* @{ |
|
*/ |
|
|
|
/** @brief Enables or disables the AHB1 peripheral clock. |
|
* @note After reset, the peripheral clock (used for registers read/write access) |
|
* is disabled and the application software has to enable this clock before |
|
* using it. |
|
*/ |
|
#define __HAL_RCC_BKPSRAM_CLK_ENABLE() do { \ |
|
__IO uint32_t tmpreg; \ |
|
SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\ |
|
/* Delay after an RCC peripheral clock enabling */ \ |
|
tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\ |
|
UNUSED(tmpreg); \ |
|
} while(0) |
|
|
|
#define __HAL_RCC_DTCMRAMEN_CLK_ENABLE() do { \ |
|
__IO uint32_t tmpreg; \ |
|
SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DTCMRAMEN);\ |
|
/* Delay after an RCC peripheral clock enabling */ \ |
|
tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DTCMRAMEN);\ |
|
UNUSED(tmpreg); \ |
|
} while(0) |
|
|
|
#define __HAL_RCC_DMA2_CLK_ENABLE() do { \ |
|
__IO uint32_t tmpreg; \ |
|
SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN);\ |
|
/* Delay after an RCC peripheral clock enabling */ \ |
|
tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN);\ |
|
UNUSED(tmpreg); \ |
|
} while(0) |
|
|
|
#define __HAL_RCC_USB_OTG_HS_CLK_ENABLE() do { \ |
|
__IO uint32_t tmpreg; \ |
|
SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\ |
|
/* Delay after an RCC peripheral clock enabling */ \ |
|
tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\ |
|
UNUSED(tmpreg); \ |
|
} while(0) |
|
|
|
#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE() do { \ |
|
__IO uint32_t tmpreg; \ |
|
SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\ |
|
/* Delay after an RCC peripheral clock enabling */ \ |
|
tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\ |
|
UNUSED(tmpreg); \ |
|
} while(0) |
|
|
|
#define __HAL_RCC_GPIOA_CLK_ENABLE() do { \ |
|
__IO uint32_t tmpreg; \ |
|
SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOAEN);\ |
|
/* Delay after an RCC peripheral clock enabling */ \ |
|
tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOAEN);\ |
|
UNUSED(tmpreg); \ |
|
} while(0) |
|
|
|
#define __HAL_RCC_GPIOB_CLK_ENABLE() do { \ |
|
__IO uint32_t tmpreg; \ |
|
SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOBEN);\ |
|
/* Delay after an RCC peripheral clock enabling */ \ |
|
tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOBEN);\ |
|
UNUSED(tmpreg); \ |
|
} while(0) |
|
|
|
#define __HAL_RCC_GPIOC_CLK_ENABLE() do { \ |
|
__IO uint32_t tmpreg; \ |
|
SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN);\ |
|
/* Delay after an RCC peripheral clock enabling */ \ |
|
tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN);\ |
|
UNUSED(tmpreg); \ |
|
} while(0) |
|
|
|
#define __HAL_RCC_GPIOD_CLK_ENABLE() do { \ |
|
__IO uint32_t tmpreg; \ |
|
SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\ |
|
/* Delay after an RCC peripheral clock enabling */ \ |
|
tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\ |
|
UNUSED(tmpreg); \ |
|
} while(0) |
|
|
|
#define __HAL_RCC_GPIOE_CLK_ENABLE() do { \ |
|
__IO uint32_t tmpreg; \ |
|
SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\ |
|
/* Delay after an RCC peripheral clock enabling */ \ |
|
tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\ |
|
UNUSED(tmpreg); \ |
|
} while(0) |
|
|
|
#define __HAL_RCC_GPIOF_CLK_ENABLE() do { \ |
|
__IO uint32_t tmpreg; \ |
|
SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\ |
|
/* Delay after an RCC peripheral clock enabling */ \ |
|
tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\ |
|
UNUSED(tmpreg); \ |
|
} while(0) |
|
|
|
#define __HAL_RCC_GPIOG_CLK_ENABLE() do { \ |
|
__IO uint32_t tmpreg; \ |
|
SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\ |
|
/* Delay after an RCC peripheral clock enabling */ \ |
|
tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\ |
|
UNUSED(tmpreg); \ |
|
} while(0) |
|
|
|
#define __HAL_RCC_GPIOH_CLK_ENABLE() do { \ |
|
__IO uint32_t tmpreg; \ |
|
SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOHEN);\ |
|
/* Delay after an RCC peripheral clock enabling */ \ |
|
tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOHEN);\ |
|
UNUSED(tmpreg); \ |
|
} while(0) |
|
|
|
#define __HAL_RCC_GPIOI_CLK_ENABLE() do { \ |
|
__IO uint32_t tmpreg; \ |
|
SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOIEN);\ |
|
/* Delay after an RCC peripheral clock enabling */ \ |
|
tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOIEN);\ |
|
UNUSED(tmpreg); \ |
|
} while(0) |
|
|
|
#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ |
|
defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\ |
|
defined (STM32F750xx) |
|
#define __HAL_RCC_GPIOJ_CLK_ENABLE() do { \ |
|
__IO uint32_t tmpreg; \ |
|
SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOJEN);\ |
|
/* Delay after an RCC peripheral clock enabling */ \ |
|
tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOJEN);\ |
|
UNUSED(tmpreg); \ |
|
} while(0) |
|
|
|
#define __HAL_RCC_GPIOK_CLK_ENABLE() do { \ |
|
__IO uint32_t tmpreg; \ |
|
SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOKEN);\ |
|
/* Delay after an RCC peripheral clock enabling */ \ |
|
tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOKEN);\ |
|
UNUSED(tmpreg); \ |
|
} while(0) |
|
|
|
#define __HAL_RCC_DMA2D_CLK_ENABLE() do { \ |
|
__IO uint32_t tmpreg; \ |
|
SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN);\ |
|
/* Delay after an RCC peripheral clock enabling */ \ |
|
tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN);\ |
|
UNUSED(tmpreg); \ |
|
} while(0) |
|
#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ |
|
|
|
#define __HAL_RCC_BKPSRAM_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_BKPSRAMEN)) |
|
#define __HAL_RCC_DTCMRAMEN_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DTCMRAMEN)) |
|
#define __HAL_RCC_DMA2_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA2EN)) |
|
#define __HAL_RCC_USB_OTG_HS_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSEN)) |
|
#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSULPIEN)) |
|
#define __HAL_RCC_GPIOA_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOAEN)) |
|
#define __HAL_RCC_GPIOB_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOBEN)) |
|
#define __HAL_RCC_GPIOC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOCEN)) |
|
#define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIODEN)) |
|
#define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOEEN)) |
|
#define __HAL_RCC_GPIOF_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOFEN)) |
|
#define __HAL_RCC_GPIOG_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOGEN)) |
|
#define __HAL_RCC_GPIOH_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOHEN)) |
|
#define __HAL_RCC_GPIOI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOIEN)) |
|
#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ |
|
defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\ |
|
defined (STM32F750xx) |
|
#define __HAL_RCC_GPIOJ_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOJEN)) |
|
#define __HAL_RCC_GPIOK_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOKEN)) |
|
#define __HAL_RCC_DMA2D_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA2DEN)) |
|
#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ |
|
|
|
#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ |
|
defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\ |
|
defined (STM32F750xx) |
|
/** |
|
* @brief Enable ETHERNET clock. |
|
*/ |
|
#define __HAL_RCC_ETHMAC_CLK_ENABLE() do { \ |
|
__IO uint32_t tmpreg; \ |
|
SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACEN);\ |
|
/* Delay after an RCC peripheral clock enabling */ \ |
|
tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACEN);\ |
|
UNUSED(tmpreg); \ |
|
} while(0) |
|
|
|
#define __HAL_RCC_ETHMACTX_CLK_ENABLE() do { \ |
|
__IO uint32_t tmpreg; \ |
|
SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACTXEN);\ |
|
/* Delay after an RCC peripheral clock enabling */ \ |
|
tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACTXEN);\ |
|
UNUSED(tmpreg); \ |
|
} while(0) |
|
|
|
#define __HAL_RCC_ETHMACRX_CLK_ENABLE() do { \ |
|
__IO uint32_t tmpreg; \ |
|
SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACRXEN);\ |
|
/* Delay after an RCC peripheral clock enabling */ \ |
|
tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACRXEN);\ |
|
UNUSED(tmpreg); \ |
|
} while(0) |
|
|
|
#define __HAL_RCC_ETHMACPTP_CLK_ENABLE() do { \ |
|
__IO uint32_t tmpreg; \ |
|
SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACPTPEN);\ |
|
/* Delay after an RCC peripheral clock enabling */ \ |
|
tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACPTPEN);\ |
|
UNUSED(tmpreg); \ |
|
} while(0) |
|
|
|
#define __HAL_RCC_ETH_CLK_ENABLE() do { \ |
|
__HAL_RCC_ETHMAC_CLK_ENABLE(); \ |
|
__HAL_RCC_ETHMACTX_CLK_ENABLE(); \ |
|
__HAL_RCC_ETHMACRX_CLK_ENABLE(); \ |
|
} while(0) |
|
/** |
|
* @brief Disable ETHERNET clock. |
|
*/ |
|
#define __HAL_RCC_ETHMAC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACEN)) |
|
#define __HAL_RCC_ETHMACTX_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACTXEN)) |
|
#define __HAL_RCC_ETHMACRX_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACRXEN)) |
|
#define __HAL_RCC_ETHMACPTP_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACPTPEN)) |
|
#define __HAL_RCC_ETH_CLK_DISABLE() do { \ |
|
__HAL_RCC_ETHMACTX_CLK_DISABLE(); \ |
|
__HAL_RCC_ETHMACRX_CLK_DISABLE(); \ |
|
__HAL_RCC_ETHMAC_CLK_DISABLE(); \ |
|
} while(0) |
|
#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ |
|
|
|
/** @brief Enable or disable the AHB2 peripheral clock. |
|
* @note After reset, the peripheral clock (used for registers read/write access) |
|
* is disabled and the application software has to enable this clock before |
|
* using it. |
|
*/ |
|
#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ |
|
defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\ |
|
defined (STM32F750xx) |
|
#define __HAL_RCC_DCMI_CLK_ENABLE() do { \ |
|
__IO uint32_t tmpreg; \ |
|
SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\ |
|
/* Delay after an RCC peripheral clock enabling */ \ |
|
tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\ |
|
UNUSED(tmpreg); \ |
|
} while(0) |
|
#define __HAL_RCC_DCMI_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_DCMIEN)) |
|
#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ |
|
|
|
#if defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) |
|
#define __HAL_RCC_JPEG_CLK_ENABLE() do { \ |
|
__IO uint32_t tmpreg; \ |
|
SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_JPEGEN);\ |
|
/* Delay after an RCC peripheral clock enabling */ \ |
|
tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_JPEGEN);\ |
|
UNUSED(tmpreg); \ |
|
} while(0) |
|
#define __HAL_RCC_JPEG_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_JPEGEN)) |
|
#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ |
|
|
|
#define __HAL_RCC_RNG_CLK_ENABLE() do { \ |
|
__IO uint32_t tmpreg; \ |
|
SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\ |
|
/* Delay after an RCC peripheral clock enabling */ \ |
|
tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\ |
|
UNUSED(tmpreg); \ |
|
} while(0) |
|
|
|
#define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() do { \ |
|
__IO uint32_t tmpreg; \ |
|
SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OTGFSEN);\ |
|
/* Delay after an RCC peripheral clock enabling */ \ |
|
tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OTGFSEN);\ |
|
UNUSED(tmpreg); \ |
|
__HAL_RCC_SYSCFG_CLK_ENABLE();\ |
|
} while(0) |
|
|
|
#define __HAL_RCC_RNG_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_RNGEN)) |
|
|
|
#define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_OTGFSEN)) |
|
#if defined(STM32F756xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx) |
|
#define __HAL_RCC_CRYP_CLK_ENABLE() do { \ |
|
__IO uint32_t tmpreg; \ |
|
SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\ |
|
/* Delay after an RCC peripheral clock enabling */ \ |
|
tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\ |
|
UNUSED(tmpreg); \ |
|
} while(0) |
|
|
|
#define __HAL_RCC_HASH_CLK_ENABLE() do { \ |
|
__IO uint32_t tmpreg; \ |
|
SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN);\ |
|
/* Delay after an RCC peripheral clock enabling */ \ |
|
tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN);\ |
|
UNUSED(tmpreg); \ |
|
} while(0) |
|
|
|
#define __HAL_RCC_CRYP_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_CRYPEN)) |
|
#define __HAL_RCC_HASH_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_HASHEN)) |
|
#endif /* STM32F756x || STM32F777xx || STM32F779xx || STM32F750xx */ |
|
|
|
#if defined(STM32F732xx) || defined (STM32F733xx) || defined (STM32F730xx) |
|
#define __HAL_RCC_AES_CLK_ENABLE() do { \ |
|
__IO uint32_t tmpreg; \ |
|
SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN);\ |
|
/* Delay after an RCC peripheral clock enabling */ \ |
|
tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN);\ |
|
UNUSED(tmpreg); \ |
|
} while(0) |
|
|
|
#define __HAL_RCC_AES_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_AESEN)) |
|
#endif /* STM32F732xx || STM32F733xx || STM32F730xx */ |
|
|
|
/** @brief Enables or disables the AHB3 peripheral clock. |
|
* @note After reset, the peripheral clock (used for registers read/write access) |
|
* is disabled and the application software has to enable this clock before |
|
* using it. |
|
*/ |
|
#define __HAL_RCC_FMC_CLK_ENABLE() do { \ |
|
__IO uint32_t tmpreg; \ |
|
SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);\ |
|
/* Delay after an RCC peripheral clock enabling */ \ |
|
tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);\ |
|
UNUSED(tmpreg); \ |
|
} while(0) |
|
|
|
#define __HAL_RCC_QSPI_CLK_ENABLE() do { \ |
|
__IO uint32_t tmpreg; \ |
|
SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\ |
|
/* Delay after an RCC peripheral clock enabling */ \ |
|
tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\ |
|
UNUSED(tmpreg); \ |
|
} while(0) |
|
|
|
#define __HAL_RCC_FMC_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_FMCEN)) |
|
#define __HAL_RCC_QSPI_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_QSPIEN)) |
|
|
|
/** @brief Enable or disable the Low Speed APB (APB1) peripheral clock. |
|
* @note After reset, the peripheral clock (used for registers read/write access) |
|
* is disabled and the application software has to enable this clock before |
|
* using it. |
|
*/ |
|
#define __HAL_RCC_TIM2_CLK_ENABLE() do { \ |
|
__IO uint32_t tmpreg; \ |
|
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\ |
|
/* Delay after an RCC peripheral clock enabling */ \ |
|
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\ |
|
UNUSED(tmpreg); \ |
|
} while(0) |
|
|
|
#define __HAL_RCC_TIM3_CLK_ENABLE() do { \ |
|
__IO uint32_t tmpreg; \ |
|
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\ |
|
/* Delay after an RCC peripheral clock enabling */ \ |
|
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\ |
|
UNUSED(tmpreg); \ |
|
} while(0) |
|
|
|
#define __HAL_RCC_TIM4_CLK_ENABLE() do { \ |
|
__IO uint32_t tmpreg; \ |
|
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\ |
|
/* Delay after an RCC peripheral clock enabling */ \ |
|
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\ |
|
UNUSED(tmpreg); \ |
|
} while(0) |
|
|
|
#define __HAL_RCC_TIM5_CLK_ENABLE() do { \ |
|
__IO uint32_t tmpreg; \ |
|
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\ |
|
/* Delay after an RCC peripheral clock enabling */ \ |
|
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\ |
|
UNUSED(tmpreg); \ |
|
} while(0) |
|
|
|
#define __HAL_RCC_TIM6_CLK_ENABLE() do { \ |
|
__IO uint32_t tmpreg; \ |
|
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\ |
|
/* Delay after an RCC peripheral clock enabling */ \ |
|
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\ |
|
UNUSED(tmpreg); \ |
|
} while(0) |
|
|
|
#define __HAL_RCC_TIM7_CLK_ENABLE() do { \ |
|
__IO uint32_t tmpreg; \ |
|
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\ |
|
/* Delay after an RCC peripheral clock enabling */ \ |
|
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\ |
|
UNUSED(tmpreg); \ |
|
} while(0) |
|
|
|
#define __HAL_RCC_TIM12_CLK_ENABLE() do { \ |
|
__IO uint32_t tmpreg; \ |
|
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\ |
|
/* Delay after an RCC peripheral clock enabling */ \ |
|
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\ |
|
UNUSED(tmpreg); \ |
|
} while(0) |
|
|
|
#define __HAL_RCC_TIM13_CLK_ENABLE() do { \ |
|
__IO uint32_t tmpreg; \ |
|
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\ |
|
/* Delay after an RCC peripheral clock enabling */ \ |
|
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\ |
|
UNUSED(tmpreg); \ |
|
} while(0) |
|
|
|
#define __HAL_RCC_TIM14_CLK_ENABLE() do { \ |
|
__IO uint32_t tmpreg; \ |
|
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\ |
|
/* Delay after an RCC peripheral clock enabling */ \ |
|
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\ |
|
UNUSED(tmpreg); \ |
|
} while(0) |
|
|
|
#define __HAL_RCC_LPTIM1_CLK_ENABLE() do { \ |
|
__IO uint32_t tmpreg; \ |
|
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_LPTIM1EN);\ |
|
/* Delay after an RCC peripheral clock enabling */ \ |
|
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_LPTIM1EN);\ |
|
UNUSED(tmpreg); \ |
|
} while(0) |
|
|
|
#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) ||\ |
|
defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) ||\ |
|
defined (STM32F779xx) || defined (STM32F730xx) |
|
#define __HAL_RCC_RTC_CLK_ENABLE() do { \ |
|
__IO uint32_t tmpreg; \ |
|
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_RTCEN);\ |
|
/* Delay after an RCC peripheral clock enabling */ \ |
|
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_RTCEN);\ |
|
UNUSED(tmpreg); \ |
|
} while(0) |
|
#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || |
|
STM32F769xx || STM32F777xx || STM32F779xx || STM32F730xx */ |
|
|
|
#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) |
|
#define __HAL_RCC_CAN3_CLK_ENABLE() do { \ |
|
__IO uint32_t tmpreg; \ |
|
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN3EN);\ |
|
/* Delay after an RCC peripheral clock enabling */ \ |
|
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN3EN);\ |
|
UNUSED(tmpreg); \ |
|
} while(0) |
|
#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ |
|
|
|
#define __HAL_RCC_SPI2_CLK_ENABLE() do { \ |
|
__IO uint32_t tmpreg; \ |
|
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\ |
|
/* Delay after an RCC peripheral clock enabling */ \ |
|
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\ |
|
UNUSED(tmpreg); \ |
|
} while(0) |
|
|
|
#define __HAL_RCC_SPI3_CLK_ENABLE() do { \ |
|
__IO uint32_t tmpreg; \ |
|
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\ |
|
/* Delay after an RCC peripheral clock enabling */ \ |
|
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\ |
|
UNUSED(tmpreg); \ |
|
} while(0) |
|
|
|
#define __HAL_RCC_USART2_CLK_ENABLE() do { \ |
|
__IO uint32_t tmpreg; \ |
|
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\ |
|
/* Delay after an RCC peripheral clock enabling */ \ |
|
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\ |
|
UNUSED(tmpreg); \ |
|
} while(0) |
|
|
|
#define __HAL_RCC_USART3_CLK_ENABLE() do { \ |
|
__IO uint32_t tmpreg; \ |
|
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\ |
|
/* Delay after an RCC peripheral clock enabling */ \ |
|
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\ |
|
UNUSED(tmpreg); \ |
|
} while(0) |
|
|
|
#define __HAL_RCC_UART4_CLK_ENABLE() do { \ |
|
__IO uint32_t tmpreg; \ |
|
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\ |
|
/* Delay after an RCC peripheral clock enabling */ \ |
|
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\ |
|
UNUSED(tmpreg); \ |
|
} while(0) |
|
|
|
#define __HAL_RCC_UART5_CLK_ENABLE() do { \ |
|
__IO uint32_t tmpreg; \ |
|
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\ |
|
/* Delay after an RCC peripheral clock enabling */ \ |
|
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\ |
|
UNUSED(tmpreg); \ |
|
} while(0) |
|
|
|
#define __HAL_RCC_I2C1_CLK_ENABLE() do { \ |
|
__IO uint32_t tmpreg; \ |
|
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\ |
|
/* Delay after an RCC peripheral clock enabling */ \ |
|
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\ |
|
UNUSED(tmpreg); \ |
|
} while(0) |
|
|
|
#define __HAL_RCC_I2C2_CLK_ENABLE() do { \ |
|
__IO uint32_t tmpreg; \ |
|
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\ |
|
/* Delay after an RCC peripheral clock enabling */ \ |
|
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\ |
|
UNUSED(tmpreg); \ |
|
} while(0) |
|
|
|
#define __HAL_RCC_I2C3_CLK_ENABLE() do { \ |
|
__IO uint32_t tmpreg; \ |
|
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\ |
|
/* Delay after an RCC peripheral clock enabling */ \ |
|
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\ |
|
UNUSED(tmpreg); \ |
|
} while(0) |
|
|
|
#define __HAL_RCC_CAN1_CLK_ENABLE() do { \ |
|
__IO uint32_t tmpreg; \ |
|
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\ |
|
/* Delay after an RCC peripheral clock enabling */ \ |
|
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\ |
|
UNUSED(tmpreg); \ |
|
} while(0) |
|
|
|
#define __HAL_RCC_DAC_CLK_ENABLE() do { \ |
|
__IO uint32_t tmpreg; \ |
|
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\ |
|
/* Delay after an RCC peripheral clock enabling */ \ |
|
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\ |
|
UNUSED(tmpreg); \ |
|
} while(0) |
|
|
|
#define __HAL_RCC_UART7_CLK_ENABLE() do { \ |
|
__IO uint32_t tmpreg; \ |
|
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART7EN);\ |
|
/* Delay after an RCC peripheral clock enabling */ \ |
|
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART7EN);\ |
|
UNUSED(tmpreg); \ |
|
} while(0) |
|
|
|
#define __HAL_RCC_UART8_CLK_ENABLE() do { \ |
|
__IO uint32_t tmpreg; \ |
|
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART8EN);\ |
|
/* Delay after an RCC peripheral clock enabling */ \ |
|
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART8EN);\ |
|
UNUSED(tmpreg); \ |
|
} while(0) |
|
|
|
#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ |
|
defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\ |
|
defined (STM32F750xx) |
|
#define __HAL_RCC_SPDIFRX_CLK_ENABLE() do { \ |
|
__IO uint32_t tmpreg; \ |
|
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPDIFRXEN);\ |
|
/* Delay after an RCC peripheral clock enabling */ \ |
|
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPDIFRXEN);\ |
|
UNUSED(tmpreg); \ |
|
} while(0) |
|
|
|
#define __HAL_RCC_I2C4_CLK_ENABLE() do { \ |
|
__IO uint32_t tmpreg; \ |
|
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C4EN);\ |
|
/* Delay after an RCC peripheral clock enabling */ \ |
|
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C4EN);\ |
|
UNUSED(tmpreg); \ |
|
} while(0) |
|
|
|
#define __HAL_RCC_CAN2_CLK_ENABLE() do { \ |
|
__IO uint32_t tmpreg; \ |
|
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\ |
|
/* Delay after an RCC peripheral clock enabling */ \ |
|
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\ |
|
UNUSED(tmpreg); \ |
|
} while(0) |
|
|
|
#define __HAL_RCC_CEC_CLK_ENABLE() do { \ |
|
__IO uint32_t tmpreg; \ |
|
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CECEN);\ |
|
/* Delay after an RCC peripheral clock enabling */ \ |
|
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CECEN);\ |
|
UNUSED(tmpreg); \ |
|
} while(0) |
|
#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ |
|
|
|
#define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN)) |
|
#define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN)) |
|
#define __HAL_RCC_TIM4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN)) |
|
#define __HAL_RCC_TIM5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM5EN)) |
|
#define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN)) |
|
#define __HAL_RCC_TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN)) |
|
#define __HAL_RCC_TIM12_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN)) |
|
#define __HAL_RCC_TIM13_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN)) |
|
#define __HAL_RCC_TIM14_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN)) |
|
#define __HAL_RCC_LPTIM1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_LPTIM1EN)) |
|
#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) ||\ |
|
defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) ||\ |
|
defined (STM32F779xx) || defined (STM32F730xx) |
|
#define __HAL_RCC_RTC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_RTCEN)) |
|
#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || |
|
STM32F769xx || STM32F777xx || STM32F779xx || STM32F730xx */ |
|
#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) |
|
#define __HAL_RCC_CAN3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN3EN)) |
|
#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ |
|
#define __HAL_RCC_SPI2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI2EN)) |
|
#define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN)) |
|
#define __HAL_RCC_USART2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART2EN)) |
|
#define __HAL_RCC_USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN)) |
|
#define __HAL_RCC_UART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN)) |
|
#define __HAL_RCC_UART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN)) |
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#define __HAL_RCC_I2C1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C1EN)) |
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#define __HAL_RCC_I2C2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN)) |
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#define __HAL_RCC_I2C3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN)) |
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#define __HAL_RCC_CAN1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN1EN)) |
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#define __HAL_RCC_DAC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN)) |
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#define __HAL_RCC_UART7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART7EN)) |
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#define __HAL_RCC_UART8_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART8EN)) |
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#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ |
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defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\ |
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defined (STM32F750xx) |
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#define __HAL_RCC_SPDIFRX_CLK_DISABLE()(RCC->APB1ENR &= ~(RCC_APB1ENR_SPDIFRXEN)) |
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#define __HAL_RCC_I2C4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C4EN)) |
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#define __HAL_RCC_CAN2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN2EN)) |
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#define __HAL_RCC_CEC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CECEN)) |
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#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || || STM32F750xx */ |
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/** @brief Enable or disable the High Speed APB (APB2) peripheral clock. |
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* @note After reset, the peripheral clock (used for registers read/write access) |
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* is disabled and the application software has to enable this clock before |
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* using it. |
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*/ |
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#define __HAL_RCC_TIM1_CLK_ENABLE() do { \ |
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__IO uint32_t tmpreg; \ |
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SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\ |
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/* Delay after an RCC peripheral clock enabling */ \ |
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tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\ |
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UNUSED(tmpreg); \ |
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} while(0) |
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|
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#define __HAL_RCC_TIM8_CLK_ENABLE() do { \ |
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__IO uint32_t tmpreg; \ |
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SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\ |
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/* Delay after an RCC peripheral clock enabling */ \ |
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tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\ |
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UNUSED(tmpreg); \ |
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} while(0) |
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|
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#define __HAL_RCC_USART1_CLK_ENABLE() do { \ |
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__IO uint32_t tmpreg; \ |
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SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\ |
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/* Delay after an RCC peripheral clock enabling */ \ |
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tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\ |
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UNUSED(tmpreg); \ |
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} while(0) |
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|
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#define __HAL_RCC_USART6_CLK_ENABLE() do { \ |
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__IO uint32_t tmpreg; \ |
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SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART6EN);\ |
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/* Delay after an RCC peripheral clock enabling */ \ |
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tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART6EN);\ |
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UNUSED(tmpreg); \ |
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} while(0) |
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|
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#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F765xx) ||\ |
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defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F730xx) |
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#define __HAL_RCC_SDMMC2_CLK_ENABLE() do { \ |
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__IO uint32_t tmpreg; \ |
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SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC2EN);\ |
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/* Delay after an RCC peripheral clock enabling */ \ |
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tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC2EN);\ |
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UNUSED(tmpreg); \ |
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} while(0) |
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#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || || STM32F730xx */ |
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#define __HAL_RCC_ADC1_CLK_ENABLE() do { \ |
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__IO uint32_t tmpreg; \ |
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SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\ |
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/* Delay after an RCC peripheral clock enabling */ \ |
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tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\ |
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UNUSED(tmpreg); \ |
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} while(0) |
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|
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#define __HAL_RCC_ADC2_CLK_ENABLE() do { \ |
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__IO uint32_t tmpreg; \ |
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SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\ |
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/* Delay after an RCC peripheral clock enabling */ \ |
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tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\ |
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UNUSED(tmpreg); \ |
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} while(0) |
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|
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#define __HAL_RCC_ADC3_CLK_ENABLE() do { \ |
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__IO uint32_t tmpreg; \ |
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SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\ |
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/* Delay after an RCC peripheral clock enabling */ \ |
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tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\ |
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UNUSED(tmpreg); \ |
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} while(0) |
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|
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#define __HAL_RCC_SDMMC1_CLK_ENABLE() do { \ |
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__IO uint32_t tmpreg; \ |
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SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC1EN);\ |
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/* Delay after an RCC peripheral clock enabling */ \ |
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tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC1EN);\ |
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UNUSED(tmpreg); \ |
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} while(0) |
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|
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#define __HAL_RCC_SPI1_CLK_ENABLE() do { \ |
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__IO uint32_t tmpreg; \ |
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SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\ |
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/* Delay after an RCC peripheral clock enabling */ \ |
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tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\ |
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UNUSED(tmpreg); \ |
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} while(0) |
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|
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#define __HAL_RCC_SPI4_CLK_ENABLE() do { \ |
|
__IO uint32_t tmpreg; \ |
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SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\ |
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/* Delay after an RCC peripheral clock enabling */ \ |
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tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\ |
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UNUSED(tmpreg); \ |
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} while(0) |
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|
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#define __HAL_RCC_TIM9_CLK_ENABLE() do { \ |
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__IO uint32_t tmpreg; \ |
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SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN);\ |
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/* Delay after an RCC peripheral clock enabling */ \ |
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tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN);\ |
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UNUSED(tmpreg); \ |
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} while(0) |
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|
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#define __HAL_RCC_TIM10_CLK_ENABLE() do { \ |
|
__IO uint32_t tmpreg; \ |
|
SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\ |
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/* Delay after an RCC peripheral clock enabling */ \ |
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tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\ |
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UNUSED(tmpreg); \ |
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} while(0) |
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|
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#define __HAL_RCC_TIM11_CLK_ENABLE() do { \ |
|
__IO uint32_t tmpreg; \ |
|
SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM11EN);\ |
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/* Delay after an RCC peripheral clock enabling */ \ |
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tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM11EN);\ |
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UNUSED(tmpreg); \ |
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} while(0) |
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|
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#define __HAL_RCC_SPI5_CLK_ENABLE() do { \ |
|
__IO uint32_t tmpreg; \ |
|
SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\ |
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/* Delay after an RCC peripheral clock enabling */ \ |
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tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\ |
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UNUSED(tmpreg); \ |
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} while(0) |
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|
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#define __HAL_RCC_SPI6_CLK_ENABLE() do { \ |
|
__IO uint32_t tmpreg; \ |
|
SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI6EN);\ |
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/* Delay after an RCC peripheral clock enabling */ \ |
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tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI6EN);\ |
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UNUSED(tmpreg); \ |
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} while(0) |
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|
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#define __HAL_RCC_SAI1_CLK_ENABLE() do { \ |
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__IO uint32_t tmpreg; \ |
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SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\ |
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/* Delay after an RCC peripheral clock enabling */ \ |
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tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\ |
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UNUSED(tmpreg); \ |
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} while(0) |
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|
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#define __HAL_RCC_SAI2_CLK_ENABLE() do { \ |
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__IO uint32_t tmpreg; \ |
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SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN);\ |
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/* Delay after an RCC peripheral clock enabling */ \ |
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tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN);\ |
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UNUSED(tmpreg); \ |
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} while(0) |
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|
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#if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx) |
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#define __HAL_RCC_LTDC_CLK_ENABLE() do { \ |
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__IO uint32_t tmpreg; \ |
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SET_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN);\ |
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/* Delay after an RCC peripheral clock enabling */ \ |
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tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN);\ |
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UNUSED(tmpreg); \ |
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} while(0) |
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#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ |
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|
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#if defined (STM32F769xx) || defined (STM32F779xx) |
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#define __HAL_RCC_DSI_CLK_ENABLE() do { \ |
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__IO uint32_t tmpreg; \ |
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SET_BIT(RCC->APB2ENR, RCC_APB2ENR_DSIEN);\ |
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/* Delay after an RCC peripheral clock enabling */ \ |
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tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DSIEN);\ |
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UNUSED(tmpreg); \ |
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} while(0) |
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#endif /* STM32F769xx || STM32F779xx */ |
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#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) |
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#define __HAL_RCC_DFSDM1_CLK_ENABLE() do { \ |
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__IO uint32_t tmpreg; \ |
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SET_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN);\ |
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/* Delay after an RCC peripheral clock enabling */ \ |
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tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN);\ |
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UNUSED(tmpreg); \ |
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} while(0) |
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|
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#define __HAL_RCC_MDIO_CLK_ENABLE() do { \ |
|
__IO uint32_t tmpreg; \ |
|
SET_BIT(RCC->APB2ENR, RCC_APB2ENR_MDIOEN);\ |
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/* Delay after an RCC peripheral clock enabling */ \ |
|
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_MDIOEN);\ |
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UNUSED(tmpreg); \ |
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} while(0) |
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#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ |
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#if defined (STM32F723xx) || defined (STM32F733xx) || defined (STM32F730xx) |
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#define __HAL_RCC_OTGPHYC_CLK_ENABLE() do { \ |
|
__IO uint32_t tmpreg; \ |
|
SET_BIT(RCC->APB2ENR, RCC_APB2ENR_OTGPHYCEN);\ |
|
/* Delay after an RCC peripheral clock enabling */ \ |
|
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_OTGPHYCEN);\ |
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UNUSED(tmpreg); \ |
|
} while(0) |
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#endif /* STM32F723xx || STM32F733xx || STM32F730xx */ |
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|
|
#define __HAL_RCC_TIM1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM1EN)) |
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#define __HAL_RCC_TIM8_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM8EN)) |
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#define __HAL_RCC_USART1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART1EN)) |
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#define __HAL_RCC_USART6_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART6EN)) |
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#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F765xx) ||\ |
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defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F730xx) |
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#define __HAL_RCC_SDMMC2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDMMC2EN)) |
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#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F730xx */ |
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#define __HAL_RCC_ADC1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC1EN)) |
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#define __HAL_RCC_ADC2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC2EN)) |
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#define __HAL_RCC_ADC3_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC3EN)) |
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#define __HAL_RCC_SDMMC1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDMMC1EN)) |
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#define __HAL_RCC_SPI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN)) |
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#define __HAL_RCC_SPI4_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI4EN)) |
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#define __HAL_RCC_TIM9_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM9EN)) |
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#define __HAL_RCC_TIM10_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN)) |
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#define __HAL_RCC_TIM11_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM11EN)) |
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#define __HAL_RCC_SPI5_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI5EN)) |
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#define __HAL_RCC_SPI6_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI6EN)) |
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#define __HAL_RCC_SAI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SAI1EN)) |
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#define __HAL_RCC_SAI2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SAI2EN)) |
|
#if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx) |
|
#define __HAL_RCC_LTDC_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_LTDCEN)) |
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#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ |
|
#if defined (STM32F769xx) || defined (STM32F779xx) |
|
#define __HAL_RCC_DSI_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_DSIEN)) |
|
#endif /* STM32F769xx || STM32F779xx */ |
|
#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) |
|
#define __HAL_RCC_DFSDM1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_DFSDM1EN)) |
|
#define __HAL_RCC_MDIO_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_MDIOEN)) |
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#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ |
|
#if defined (STM32F723xx) || defined (STM32F733xx) || defined (STM32F730xx) |
|
#define __HAL_RCC_OTGPHYC_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_OTGPHYCEN)) |
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#endif /* STM32F723xx || STM32F733xx || STM32F730xx */ |
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|
|
/** |
|
* @} |
|
*/ |
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|
|
/** @defgroup RCCEx_Peripheral_Clock_Enable_Disable_Status Peripheral Clock Enable Disable Status |
|
* @brief Get the enable or disable status of the AHB/APB peripheral clock. |
|
* @note After reset, the peripheral clock (used for registers read/write access) |
|
* is disabled and the application software has to enable this clock before |
|
* using it. |
|
* @{ |
|
*/ |
|
|
|
/** @brief Get the enable or disable status of the AHB1 peripheral clock. |
|
* @note After reset, the peripheral clock (used for registers read/write access) |
|
* is disabled and the application software has to enable this clock before |
|
* using it. |
|
*/ |
|
#define __HAL_RCC_BKPSRAM_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_BKPSRAMEN)) != RESET) |
|
#define __HAL_RCC_DTCMRAMEN_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DTCMRAMEN)) != RESET) |
|
#define __HAL_RCC_DMA2_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DMA2EN)) != RESET) |
|
#define __HAL_RCC_USB_OTG_HS_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSEN)) != RESET) |
|
#define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSULPIEN)) != RESET) |
|
#define __HAL_RCC_GPIOA_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOAEN)) != RESET) |
|
#define __HAL_RCC_GPIOB_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOBEN)) != RESET) |
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#define __HAL_RCC_GPIOC_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOCEN)) != RESET) |
|
#define __HAL_RCC_GPIOD_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) != RESET) |
|
#define __HAL_RCC_GPIOE_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) != RESET) |
|
#define __HAL_RCC_GPIOF_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) != RESET) |
|
#define __HAL_RCC_GPIOG_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) != RESET) |
|
#define __HAL_RCC_GPIOH_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOHEN)) != RESET) |
|
#define __HAL_RCC_GPIOI_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOIEN)) != RESET) |
|
#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ |
|
defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\ |
|
defined (STM32F750xx) |
|
#define __HAL_RCC_GPIOJ_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOJEN)) != RESET) |
|
#define __HAL_RCC_GPIOK_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOKEN)) != RESET) |
|
#define __HAL_RCC_DMA2D_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DMA2DEN)) != RESET) |
|
#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ |
|
|
|
#define __HAL_RCC_BKPSRAM_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_BKPSRAMEN)) == RESET) |
|
#define __HAL_RCC_DTCMRAMEN_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DTCMRAMEN)) == RESET) |
|
#define __HAL_RCC_DMA2_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DMA2EN)) == RESET) |
|
#define __HAL_RCC_USB_OTG_HS_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSEN)) == RESET) |
|
#define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSULPIEN)) == RESET) |
|
#define __HAL_RCC_GPIOA_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOAEN)) == RESET) |
|
#define __HAL_RCC_GPIOB_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOBEN)) == RESET) |
|
#define __HAL_RCC_GPIOC_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOCEN)) == RESET) |
|
#define __HAL_RCC_GPIOD_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) == RESET) |
|
#define __HAL_RCC_GPIOE_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) == RESET) |
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#define __HAL_RCC_GPIOF_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) == RESET) |
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#define __HAL_RCC_GPIOG_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) == RESET) |
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#define __HAL_RCC_GPIOH_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOHEN)) == RESET) |
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#define __HAL_RCC_GPIOI_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOIEN)) == RESET) |
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#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ |
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defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\ |
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defined (STM32F750xx) |
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#define __HAL_RCC_GPIOJ_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOJEN)) == RESET) |
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#define __HAL_RCC_GPIOK_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOKEN)) == RESET) |
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#define __HAL_RCC_DMA2D_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DMA2DEN)) == RESET) |
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#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ |
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#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ |
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defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\ |
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defined (STM32F750xx) |
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/** |
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* @brief Enable ETHERNET clock. |
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*/ |
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#define __HAL_RCC_ETHMAC_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACEN)) != RESET) |
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#define __HAL_RCC_ETHMACTX_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACTXEN)) != RESET) |
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#define __HAL_RCC_ETHMACRX_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACRXEN)) != RESET) |
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#define __HAL_RCC_ETHMACPTP_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACPTPEN)) != RESET) |
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#define __HAL_RCC_ETH_IS_CLK_ENABLED() (__HAL_RCC_ETHMAC_IS_CLK_ENABLED() && \ |
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__HAL_RCC_ETHMACTX_IS_CLK_ENABLED() && \ |
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__HAL_RCC_ETHMACRX_IS_CLK_ENABLED()) |
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|
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/** |
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* @brief Disable ETHERNET clock. |
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*/ |
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#define __HAL_RCC_ETHMAC_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACEN)) == RESET) |
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#define __HAL_RCC_ETHMACTX_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACTXEN)) == RESET) |
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#define __HAL_RCC_ETHMACRX_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACRXEN)) == RESET) |
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#define __HAL_RCC_ETHMACPTP_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACPTPEN)) == RESET) |
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#define __HAL_RCC_ETH_IS_CLK_DISABLED() (__HAL_RCC_ETHMAC_IS_CLK_DISABLED() && \ |
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__HAL_RCC_ETHMACTX_IS_CLK_DISABLED() && \ |
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__HAL_RCC_ETHMACRX_IS_CLK_DISABLED()) |
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#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ |
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|
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/** @brief Get the enable or disable status of the AHB2 peripheral clock. |
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* @note After reset, the peripheral clock (used for registers read/write access) |
|
* is disabled and the application software has to enable this clock before |
|
* using it. |
|
*/ |
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#define __HAL_RCC_RNG_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) != RESET) |
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#define __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) != RESET) |
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|
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#define __HAL_RCC_RNG_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) == RESET) |
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#define __HAL_RCC_USB_IS_OTG_FS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) == RESET) |
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|
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#if defined(STM32F756xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx) |
|
#define __HAL_RCC_CRYP_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_CRYPEN)) != RESET) |
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#define __HAL_RCC_HASH_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_HASHEN)) != RESET) |
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#define __HAL_RCC_CRYP_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_CRYPEN)) == RESET) |
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#define __HAL_RCC_HASH_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_HASHEN)) == RESET) |
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#endif /* STM32F756xx || STM32F777xx || STM32F779xx || STM32F750xx */ |
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|
|
#if defined(STM32F732xx) || defined (STM32F733xx) || defined (STM32F730xx) |
|
#define __HAL_RCC_AES_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_AESEN)) != RESET) |
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#define __HAL_RCC_AES_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_AESEN)) == RESET) |
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#endif /* STM32F732xx || STM32F733xx || STM32F730xx */ |
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|
|
#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ |
|
defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\ |
|
defined (STM32F750xx) |
|
#define __HAL_RCC_DCMI_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_DCMIEN)) != RESET) |
|
#define __HAL_RCC_DCMI_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_DCMIEN)) == RESET) |
|
#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ |
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|
|
#if defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) |
|
#define __HAL_RCC_JPEG_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_JPEGEN)) != RESET) |
|
#define __HAL_RCC_JPEG_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_JPEGEN)) == RESET) |
|
#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ |
|
|
|
/** @brief Get the enable or disable status of the AHB3 peripheral clock. |
|
* @note After reset, the peripheral clock (used for registers read/write access) |
|
* is disabled and the application software has to enable this clock before |
|
* using it. |
|
*/ |
|
#define __HAL_RCC_FMC_IS_CLK_ENABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_FMCEN)) != RESET) |
|
#define __HAL_RCC_QSPI_IS_CLK_ENABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_QSPIEN)) != RESET) |
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|
|
#define __HAL_RCC_FMC_IS_CLK_DISABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_FMCEN)) == RESET) |
|
#define __HAL_RCC_QSPI_IS_CLK_DISABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_QSPIEN)) == RESET) |
|
|
|
/** @brief Get the enable or disable status of the APB1 peripheral clock. |
|
* @note After reset, the peripheral clock (used for registers read/write access) |
|
* is disabled and the application software has to enable this clock before |
|
* using it. |
|
*/ |
|
#define __HAL_RCC_TIM2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) != RESET) |
|
#define __HAL_RCC_TIM3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET) |
|
#define __HAL_RCC_TIM4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) != RESET) |
|
#define __HAL_RCC_TIM5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) != RESET) |
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#define __HAL_RCC_TIM6_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) != RESET) |
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#define __HAL_RCC_TIM7_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) != RESET) |
|
#define __HAL_RCC_TIM12_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) != RESET) |
|
#define __HAL_RCC_TIM13_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) != RESET) |
|
#define __HAL_RCC_TIM14_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) != RESET) |
|
#define __HAL_RCC_LPTIM1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_LPTIM1EN)) != RESET) |
|
#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) |
|
#define __HAL_RCC_CAN3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN3EN)) != RESET) |
|
#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ |
|
#define __HAL_RCC_SPI2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) != RESET) |
|
#define __HAL_RCC_SPI3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET) |
|
#define __HAL_RCC_USART2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) != RESET) |
|
#define __HAL_RCC_USART3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) != RESET) |
|
#define __HAL_RCC_UART4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) != RESET) |
|
#define __HAL_RCC_UART5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) != RESET) |
|
#define __HAL_RCC_I2C1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) != RESET) |
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#define __HAL_RCC_I2C2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) != RESET) |
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#define __HAL_RCC_I2C3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) != RESET) |
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#define __HAL_RCC_CAN1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) != RESET) |
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#define __HAL_RCC_DAC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) != RESET) |
|
#define __HAL_RCC_UART7_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART7EN)) != RESET) |
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#define __HAL_RCC_UART8_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART8EN)) != RESET) |
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|
|
#define __HAL_RCC_TIM2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) == RESET) |
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#define __HAL_RCC_TIM3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET) |
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#define __HAL_RCC_TIM4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) == RESET) |
|
#define __HAL_RCC_TIM5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) == RESET) |
|
#define __HAL_RCC_TIM6_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) == RESET) |
|
#define __HAL_RCC_TIM7_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) == RESET) |
|
#define __HAL_RCC_TIM12_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) == RESET) |
|
#define __HAL_RCC_TIM13_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) == RESET) |
|
#define __HAL_RCC_TIM14_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) == RESET) |
|
#define __HAL_RCC_LPTIM1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_LPTIM1EN)) == RESET) |
|
#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) |
|
#define __HAL_RCC_CAN3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN3EN)) == RESET) |
|
#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ |
|
#define __HAL_RCC_SPI2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) == RESET) |
|
#define __HAL_RCC_SPI3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET) |
|
#define __HAL_RCC_USART2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) == RESET) |
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#define __HAL_RCC_USART3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) == RESET) |
|
#define __HAL_RCC_UART4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) == RESET) |
|
#define __HAL_RCC_UART5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) == RESET) |
|
#define __HAL_RCC_I2C1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) == RESET) |
|
#define __HAL_RCC_I2C2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) == RESET) |
|
#define __HAL_RCC_I2C3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) == RESET) |
|
#define __HAL_RCC_CAN1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) == RESET) |
|
#define __HAL_RCC_DAC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) == RESET) |
|
#define __HAL_RCC_UART7_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART7EN)) == RESET) |
|
#define __HAL_RCC_UART8_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART8EN)) == RESET) |
|
#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ |
|
defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\ |
|
defined (STM32F750xx) |
|
#define __HAL_RCC_SPDIFRX_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPDIFRXEN)) != RESET) |
|
#define __HAL_RCC_CAN2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) != RESET) |
|
#define __HAL_RCC_CEC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CECEN)) != RESET) |
|
#define __HAL_RCC_I2C4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C4EN)) != RESET) |
|
|
|
#define __HAL_RCC_SPDIFRX_IS_CLK_DISABLED()((RCC->APB1ENR & (RCC_APB1ENR_SPDIFRXEN)) == RESET) |
|
#define __HAL_RCC_CAN2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) == RESET) |
|
#define __HAL_RCC_CEC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CECEN)) == RESET) |
|
#define __HAL_RCC_I2C4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C4EN)) == RESET) |
|
#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ |
|
|
|
#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) ||\ |
|
defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) ||\ |
|
defined (STM32F779xx) || defined (STM32F730xx) |
|
#define __HAL_RCC_RTC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_RTCEN)) != RESET) |
|
#define __HAL_RCC_RTC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_RTCEN)) == RESET) |
|
#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || |
|
STM32F769xx || STM32F777xx || STM32F779xx || STM32F730xx */ |
|
|
|
/** @brief Get the enable or disable status of the APB2 peripheral clock. |
|
* @note After reset, the peripheral clock (used for registers read/write access) |
|
* is disabled and the application software has to enable this clock before |
|
* using it. |
|
*/ |
|
#define __HAL_RCC_TIM1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM1EN)) != RESET) |
|
#define __HAL_RCC_TIM8_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) != RESET) |
|
#define __HAL_RCC_USART1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) != RESET) |
|
#define __HAL_RCC_USART6_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART6EN)) != RESET) |
|
#define __HAL_RCC_ADC1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) != RESET) |
|
#define __HAL_RCC_ADC2_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) != RESET) |
|
#define __HAL_RCC_ADC3_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) != RESET) |
|
#define __HAL_RCC_SDMMC1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDMMC1EN)) != RESET) |
|
#define __HAL_RCC_SPI1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) != RESET) |
|
#define __HAL_RCC_SPI4_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) != RESET) |
|
#define __HAL_RCC_TIM9_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM9EN)) != RESET) |
|
#define __HAL_RCC_TIM10_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) != RESET) |
|
#define __HAL_RCC_TIM11_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM11EN)) != RESET) |
|
#define __HAL_RCC_SPI5_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) != RESET) |
|
#define __HAL_RCC_SPI6_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI6EN)) != RESET) |
|
#define __HAL_RCC_SAI1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI1EN)) != RESET) |
|
#define __HAL_RCC_SAI2_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI2EN)) != RESET) |
|
#if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx) |
|
#define __HAL_RCC_LTDC_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_LTDCEN)) != RESET) |
|
#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ |
|
#if defined (STM32F769xx) || defined (STM32F779xx) |
|
#define __HAL_RCC_DSI_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_DSIEN)) != RESET) |
|
#endif /* STM32F769xx || STM32F779xx */ |
|
#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F765xx) ||\ |
|
defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F730xx) |
|
#define __HAL_RCC_SDMMC2_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDMMC2EN)) != RESET) |
|
#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F730xx */ |
|
#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) |
|
#define __HAL_RCC_DFSDM1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_DFSDM1EN)) != RESET) |
|
#define __HAL_RCC_MDIO_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_MDIOEN)) != RESET) |
|
#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ |
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#if defined (STM32F723xx) || defined (STM32F733xx) || defined (STM32F730xx) |
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#define __HAL_RCC_OTGPHYC_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_OTGPHYCEN)) != RESET) |
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#endif /* STM32F723xx || STM32F733xx || STM32F730xx */ |
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#define __HAL_RCC_TIM1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM1EN)) == RESET) |
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#define __HAL_RCC_TIM8_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) == RESET) |
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#define __HAL_RCC_USART1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) == RESET) |
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#define __HAL_RCC_USART6_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART6EN)) == RESET) |
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#define __HAL_RCC_ADC1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) == RESET) |
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#define __HAL_RCC_ADC2_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) == RESET) |
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#define __HAL_RCC_ADC3_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) == RESET) |
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#define __HAL_RCC_SDMMC1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDMMC1EN)) == RESET) |
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#define __HAL_RCC_SPI1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) == RESET) |
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#define __HAL_RCC_SPI4_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) == RESET) |
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#define __HAL_RCC_TIM9_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM9EN)) == RESET) |
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#define __HAL_RCC_TIM10_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) == RESET) |
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#define __HAL_RCC_TIM11_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM11EN)) == RESET) |
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#define __HAL_RCC_SPI5_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) == RESET) |
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#define __HAL_RCC_SPI6_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI6EN)) == RESET) |
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#define __HAL_RCC_SAI1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI1EN)) == RESET) |
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#define __HAL_RCC_SAI2_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI2EN)) == RESET) |
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#if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx) |
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#define __HAL_RCC_LTDC_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_LTDCEN)) == RESET) |
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#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ |
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#if defined (STM32F769xx) || defined (STM32F779xx) |
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#define __HAL_RCC_DSI_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_DSIEN)) == RESET) |
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#endif /* STM32F769xx || STM32F779xx */ |
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#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F765xx) ||\ |
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defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F730xx) |
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#define __HAL_RCC_SDMMC2_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDMMC2EN)) == RESET) |
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#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F730xx */ |
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#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) |
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#define __HAL_RCC_DFSDM1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_DFSDM1EN)) == RESET) |
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#define __HAL_RCC_MDIO_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_MDIOEN)) == RESET) |
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#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ |
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#if defined (STM32F723xx) || defined (STM32F733xx) || defined (STM32F730xx) |
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#define __HAL_RCC_OTGPHYC_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_OTGPHYCEN)) == RESET) |
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#endif /* STM32F723xx || STM32F733xx || STM32F730xx */ |
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/** |
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* @} |
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*/ |
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/** @defgroup RCCEx_Force_Release_Peripheral_Reset RCCEx Force Release Peripheral Reset |
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* @brief Forces or releases AHB/APB peripheral reset. |
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* @{ |
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*/ |
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/** @brief Force or release AHB1 peripheral reset. |
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*/ |
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#define __HAL_RCC_DMA2_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA2RST)) |
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#define __HAL_RCC_USB_OTG_HS_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_OTGHRST)) |
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#define __HAL_RCC_GPIOA_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOARST)) |
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#define __HAL_RCC_GPIOB_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOBRST)) |
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#define __HAL_RCC_GPIOC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOCRST)) |
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#define __HAL_RCC_GPIOD_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIODRST)) |
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#define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOERST)) |
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#define __HAL_RCC_GPIOF_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOFRST)) |
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#define __HAL_RCC_GPIOG_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOGRST)) |
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#define __HAL_RCC_GPIOH_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOHRST)) |
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#define __HAL_RCC_GPIOI_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOIRST)) |
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#define __HAL_RCC_DMA2_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA2RST)) |
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#define __HAL_RCC_USB_OTG_HS_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_OTGHRST)) |
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#define __HAL_RCC_GPIOA_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOARST)) |
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#define __HAL_RCC_GPIOB_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOBRST)) |
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#define __HAL_RCC_GPIOC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOCRST)) |
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#define __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIODRST)) |
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#define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOERST)) |
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#define __HAL_RCC_GPIOF_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOFRST)) |
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#define __HAL_RCC_GPIOG_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOGRST)) |
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#define __HAL_RCC_GPIOH_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOHRST)) |
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#define __HAL_RCC_GPIOI_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOIRST)) |
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#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ |
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defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\ |
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defined (STM32F750xx) |
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#define __HAL_RCC_DMA2D_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA2DRST)) |
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#define __HAL_RCC_ETHMAC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_ETHMACRST)) |
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#define __HAL_RCC_GPIOJ_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOJRST)) |
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#define __HAL_RCC_GPIOK_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOKRST)) |
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#define __HAL_RCC_DMA2D_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA2DRST)) |
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#define __HAL_RCC_ETHMAC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_ETHMACRST)) |
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#define __HAL_RCC_GPIOJ_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOJRST)) |
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#define __HAL_RCC_GPIOK_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOKRST)) |
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#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ |
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/** @brief Force or release AHB2 peripheral reset. |
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*/ |
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#define __HAL_RCC_AHB2_FORCE_RESET() (RCC->AHB2RSTR = 0xFFFFFFFFU) |
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#define __HAL_RCC_RNG_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_RNGRST)) |
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#define __HAL_RCC_USB_OTG_FS_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_OTGFSRST)) |
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#define __HAL_RCC_AHB2_RELEASE_RESET() (RCC->AHB2RSTR = 0x00U) |
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#define __HAL_RCC_RNG_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_RNGRST)) |
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#define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_OTGFSRST)) |
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#if defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) |
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#define __HAL_RCC_JPEG_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_JPEGRST)) |
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#define __HAL_RCC_JPEG_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_JPEGRST)) |
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#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ |
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#if defined(STM32F756xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx) |
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#define __HAL_RCC_CRYP_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_CRYPRST)) |
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#define __HAL_RCC_HASH_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_HASHRST)) |
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#define __HAL_RCC_CRYP_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_CRYPRST)) |
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#define __HAL_RCC_HASH_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_HASHRST)) |
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#endif /* STM32F756xx || STM32F777xx || STM32F779xx || STM32F750xx */ |
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#if defined(STM32F732xx) || defined (STM32F733xx) || defined (STM32F730xx) |
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#define __HAL_RCC_AES_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_AESRST)) |
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#define __HAL_RCC_AES_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_AESRST)) |
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#endif /* STM32F732xx || STM32F733xx || STM32F730xx */ |
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#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ |
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defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\ |
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defined (STM32F750xx) |
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#define __HAL_RCC_DCMI_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_DCMIRST)) |
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#define __HAL_RCC_DCMI_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_DCMIRST)) |
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#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ |
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/** @brief Force or release AHB3 peripheral reset |
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*/ |
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#define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0xFFFFFFFFU) |
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#define __HAL_RCC_FMC_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_FMCRST)) |
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#define __HAL_RCC_QSPI_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_QSPIRST)) |
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#define __HAL_RCC_AHB3_RELEASE_RESET() (RCC->AHB3RSTR = 0x00U) |
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#define __HAL_RCC_FMC_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_FMCRST)) |
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#define __HAL_RCC_QSPI_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_QSPIRST)) |
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/** @brief Force or release APB1 peripheral reset. |
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*/ |
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#define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST)) |
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#define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST)) |
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#define __HAL_RCC_TIM4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM4RST)) |
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#define __HAL_RCC_TIM5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM5RST)) |
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#define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST)) |
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#define __HAL_RCC_TIM7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM7RST)) |
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#define __HAL_RCC_TIM12_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM12RST)) |
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#define __HAL_RCC_TIM13_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM13RST)) |
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#define __HAL_RCC_TIM14_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM14RST)) |
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#define __HAL_RCC_LPTIM1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_LPTIM1RST)) |
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#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) |
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#define __HAL_RCC_CAN3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN3RST)) |
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#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ |
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#define __HAL_RCC_SPI2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI2RST)) |
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#define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST)) |
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#define __HAL_RCC_USART2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART2RST)) |
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#define __HAL_RCC_USART3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART3RST)) |
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#define __HAL_RCC_UART4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART4RST)) |
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#define __HAL_RCC_UART5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART5RST)) |
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#define __HAL_RCC_I2C1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C1RST)) |
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#define __HAL_RCC_I2C2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C2RST)) |
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#define __HAL_RCC_I2C3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C3RST)) |
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#define __HAL_RCC_CAN1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN1RST)) |
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#define __HAL_RCC_DAC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_DACRST)) |
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#define __HAL_RCC_UART7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART7RST)) |
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#define __HAL_RCC_UART8_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART8RST)) |
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#define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST)) |
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#define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST)) |
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#define __HAL_RCC_TIM4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST)) |
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#define __HAL_RCC_TIM5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM5RST)) |
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#define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST)) |
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#define __HAL_RCC_TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST)) |
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#define __HAL_RCC_TIM12_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM12RST)) |
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#define __HAL_RCC_TIM13_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM13RST)) |
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#define __HAL_RCC_TIM14_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST)) |
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#define __HAL_RCC_LPTIM1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_LPTIM1RST)) |
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#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) |
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#define __HAL_RCC_CAN3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN3RST)) |
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#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ |
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#define __HAL_RCC_SPI2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI2RST)) |
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#define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST)) |
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#define __HAL_RCC_USART2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART2RST)) |
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#define __HAL_RCC_USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST)) |
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#define __HAL_RCC_UART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST)) |
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#define __HAL_RCC_UART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST)) |
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#define __HAL_RCC_I2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C1RST)) |
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#define __HAL_RCC_I2C2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C2RST)) |
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#define __HAL_RCC_I2C3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C3RST)) |
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#define __HAL_RCC_CAN1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN1RST)) |
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#define __HAL_RCC_DAC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST)) |
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#define __HAL_RCC_UART7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART7RST)) |
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#define __HAL_RCC_UART8_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART8RST)) |
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#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ |
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defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\ |
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defined (STM32F750xx) |
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#define __HAL_RCC_SPDIFRX_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPDIFRXRST)) |
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#define __HAL_RCC_I2C4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C4RST)) |
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#define __HAL_RCC_CAN2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN2RST)) |
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#define __HAL_RCC_CEC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CECRST)) |
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#define __HAL_RCC_SPDIFRX_RELEASE_RESET()(RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPDIFRXRST)) |
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#define __HAL_RCC_I2C4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C4RST)) |
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#define __HAL_RCC_CAN2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN2RST)) |
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#define __HAL_RCC_CEC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CECRST)) |
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#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ |
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/** @brief Force or release APB2 peripheral reset. |
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*/ |
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#define __HAL_RCC_TIM1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM1RST)) |
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#define __HAL_RCC_TIM8_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM8RST)) |
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#define __HAL_RCC_USART1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART1RST)) |
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#define __HAL_RCC_USART6_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART6RST)) |
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#define __HAL_RCC_ADC_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_ADCRST)) |
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#define __HAL_RCC_SDMMC1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SDMMC1RST)) |
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#define __HAL_RCC_SPI1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI1RST)) |
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#define __HAL_RCC_SPI4_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI4RST)) |
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#define __HAL_RCC_TIM9_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM9RST)) |
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#define __HAL_RCC_TIM10_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM10RST)) |
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#define __HAL_RCC_TIM11_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM11RST)) |
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#define __HAL_RCC_SPI5_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI5RST)) |
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#define __HAL_RCC_SPI6_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI6RST)) |
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#define __HAL_RCC_SAI1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SAI1RST)) |
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#define __HAL_RCC_SAI2_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SAI2RST)) |
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#if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx) |
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#define __HAL_RCC_LTDC_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_LTDCRST)) |
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#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ |
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#if defined (STM32F723xx) || defined (STM32F733xx) || defined (STM32F730xx) |
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#define __HAL_RCC_OTGPHYC_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_OTGPHYCRST)) |
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#endif /* STM32F723xx || STM32F733xx || STM32F730xx */ |
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#define __HAL_RCC_TIM1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM1RST)) |
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#define __HAL_RCC_TIM8_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM8RST)) |
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#define __HAL_RCC_USART1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART1RST)) |
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#define __HAL_RCC_USART6_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART6RST)) |
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#define __HAL_RCC_ADC_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_ADCRST)) |
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#define __HAL_RCC_SDMMC1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDMMC1RST)) |
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#define __HAL_RCC_SPI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI1RST)) |
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#define __HAL_RCC_SPI4_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI4RST)) |
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#define __HAL_RCC_TIM9_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM9RST)) |
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#define __HAL_RCC_TIM10_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST)) |
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#define __HAL_RCC_TIM11_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM11RST)) |
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#define __HAL_RCC_SPI5_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI5RST)) |
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#define __HAL_RCC_SPI6_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI6RST)) |
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#define __HAL_RCC_SAI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SAI1RST)) |
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#define __HAL_RCC_SAI2_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SAI2RST)) |
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#if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx) |
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#define __HAL_RCC_LTDC_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_LTDCRST)) |
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#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ |
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#if defined (STM32F723xx) || defined (STM32F733xx) || defined (STM32F730xx) |
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#define __HAL_RCC_OTGPHYC_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_OTGPHYCRST)) |
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#endif /* STM32F723xx || STM32F733xx || STM32F730xx */ |
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#if defined (STM32F769xx) || defined (STM32F779xx) |
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#define __HAL_RCC_DSI_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_DSIRST)) |
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#define __HAL_RCC_DSI_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_DSIRST)) |
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#endif /* STM32F769xx || STM32F779xx */ |
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#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F765xx) ||\ |
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defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F730xx) |
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#define __HAL_RCC_SDMMC2_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SDMMC2RST)) |
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#define __HAL_RCC_SDMMC2_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDMMC2RST)) |
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#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F730xx */ |
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#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) |
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#define __HAL_RCC_DFSDM1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_DFSDM1RST)) |
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#define __HAL_RCC_MDIO_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_MDIORST)) |
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#define __HAL_RCC_DFSDM1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_DFSDM1RST)) |
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#define __HAL_RCC_MDIO_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_MDIORST)) |
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#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ |
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/** |
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* @} |
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*/ |
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/** @defgroup RCCEx_Peripheral_Clock_Sleep_Enable_Disable RCCEx Peripheral Clock Sleep Enable Disable |
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* @brief Enables or disables the AHB/APB peripheral clock during Low Power (Sleep) mode. |
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* @note Peripheral clock gating in SLEEP mode can be used to further reduce |
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* power consumption. |
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* @note After wakeup from SLEEP mode, the peripheral clock is enabled again. |
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* @note By default, all peripheral clocks are enabled during SLEEP mode. |
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* @{ |
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*/ |
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|
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/** @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode. |
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*/ |
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#define __HAL_RCC_FLITF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_FLITFLPEN)) |
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#define __HAL_RCC_AXI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_AXILPEN)) |
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#define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM1LPEN)) |
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#define __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM2LPEN)) |
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#define __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_BKPSRAMLPEN)) |
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#define __HAL_RCC_DTCM_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DTCMLPEN)) |
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#define __HAL_RCC_DMA2_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA2LPEN)) |
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#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_OTGHSLPEN)) |
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#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_OTGHSULPILPEN)) |
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#define __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOALPEN)) |
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#define __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOBLPEN)) |
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#define __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOCLPEN)) |
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#define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIODLPEN)) |
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#define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOELPEN)) |
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#define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOFLPEN)) |
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#define __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOGLPEN)) |
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#define __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOHLPEN)) |
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#define __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOILPEN)) |
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#define __HAL_RCC_FLITF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_FLITFLPEN)) |
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#define __HAL_RCC_AXI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_AXILPEN)) |
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#define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM1LPEN)) |
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#define __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM2LPEN)) |
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#define __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_BKPSRAMLPEN)) |
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#define __HAL_RCC_DTCM_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DTCMLPEN)) |
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#define __HAL_RCC_DMA2_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DMA2LPEN)) |
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#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSLPEN)) |
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#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSULPILPEN)) |
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#define __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOALPEN)) |
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#define __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOBLPEN)) |
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#define __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOCLPEN)) |
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#define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIODLPEN)) |
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#define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOELPEN)) |
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#define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOFLPEN)) |
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#define __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOGLPEN)) |
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#define __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOHLPEN)) |
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#define __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOILPEN)) |
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#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ |
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defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\ |
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defined (STM32F750xx) |
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#define __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA2DLPEN)) |
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#define __HAL_RCC_ETHMAC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACLPEN)) |
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#define __HAL_RCC_ETHMACTX_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACTXLPEN)) |
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#define __HAL_RCC_ETHMACRX_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACRXLPEN)) |
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#define __HAL_RCC_ETHMACPTP_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACPTPLPEN)) |
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#define __HAL_RCC_GPIOJ_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOJLPEN)) |
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#define __HAL_RCC_GPIOK_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOKLPEN)) |
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#define __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DMA2DLPEN)) |
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#define __HAL_RCC_ETHMAC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACLPEN)) |
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#define __HAL_RCC_ETHMACTX_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACTXLPEN)) |
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#define __HAL_RCC_ETHMACRX_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACRXLPEN)) |
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#define __HAL_RCC_ETHMACPTP_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACPTPLPEN)) |
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#define __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOJLPEN)) |
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#define __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOKLPEN)) |
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#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ |
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/** @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode. |
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* @note Peripheral clock gating in SLEEP mode can be used to further reduce |
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* power consumption. |
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* @note After wakeup from SLEEP mode, the peripheral clock is enabled again. |
|
* @note By default, all peripheral clocks are enabled during SLEEP mode. |
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*/ |
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#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ |
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defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\ |
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defined (STM32F750xx) |
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#define __HAL_RCC_DCMI_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_DCMILPEN)) |
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#define __HAL_RCC_DCMI_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_DCMILPEN)) |
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#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ |
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#if defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) |
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#define __HAL_RCC_JPEG_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_JPEGLPEN)) |
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#define __HAL_RCC_JPEG_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_JPEGLPEN)) |
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#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ |
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#define __HAL_RCC_RNG_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_RNGLPEN)) |
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#define __HAL_RCC_RNG_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_RNGLPEN)) |
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#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_OTGFSLPEN)) |
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#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_OTGFSLPEN)) |
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#if defined(STM32F756xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx) |
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#define __HAL_RCC_CRYP_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_CRYPLPEN)) |
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#define __HAL_RCC_HASH_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_HASHLPEN)) |
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#define __HAL_RCC_CRYP_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_CRYPLPEN)) |
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#define __HAL_RCC_HASH_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_HASHLPEN)) |
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#endif /* STM32F756xx || STM32F777xx || STM32F779xx || STM32F750xx */ |
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#if defined(STM32F732xx) || defined (STM32F733xx) || defined (STM32F730xx) |
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#define __HAL_RCC_AES_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_AESLPEN)) |
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#define __HAL_RCC_AES_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_AESLPEN)) |
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#endif /* STM32F732xx || STM32F733xx || STM32F730xx */ |
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/** @brief Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode. |
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* @note Peripheral clock gating in SLEEP mode can be used to further reduce |
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* power consumption. |
|
* @note After wakeup from SLEEP mode, the peripheral clock is enabled again. |
|
* @note By default, all peripheral clocks are enabled during SLEEP mode. |
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*/ |
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#define __HAL_RCC_FMC_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_FMCLPEN)) |
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#define __HAL_RCC_FMC_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_FMCLPEN)) |
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#define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_QSPILPEN)) |
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#define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_QSPILPEN)) |
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|
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/** @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode. |
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* @note Peripheral clock gating in SLEEP mode can be used to further reduce |
|
* power consumption. |
|
* @note After wakeup from SLEEP mode, the peripheral clock is enabled again. |
|
* @note By default, all peripheral clocks are enabled during SLEEP mode. |
|
*/ |
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#define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM2LPEN)) |
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#define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM3LPEN)) |
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#define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM4LPEN)) |
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#define __HAL_RCC_TIM5_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM5LPEN)) |
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#define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM6LPEN)) |
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#define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM7LPEN)) |
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#define __HAL_RCC_TIM12_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM12LPEN)) |
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#define __HAL_RCC_TIM13_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM13LPEN)) |
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#define __HAL_RCC_TIM14_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM14LPEN)) |
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#define __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_LPTIM1LPEN)) |
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#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) |
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#define __HAL_RCC_CAN3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN3LPEN)) |
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#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ |
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#define __HAL_RCC_SPI2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI2LPEN)) |
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#define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI3LPEN)) |
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#define __HAL_RCC_USART2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_USART2LPEN)) |
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#define __HAL_RCC_USART3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_USART3LPEN)) |
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#define __HAL_RCC_UART4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART4LPEN)) |
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#define __HAL_RCC_UART5_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART5LPEN)) |
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#define __HAL_RCC_I2C1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C1LPEN)) |
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#define __HAL_RCC_I2C2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C2LPEN)) |
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#define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C3LPEN)) |
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#define __HAL_RCC_CAN1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN1LPEN)) |
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#define __HAL_RCC_DAC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_DACLPEN)) |
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#define __HAL_RCC_UART7_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART7LPEN)) |
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#define __HAL_RCC_UART8_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART8LPEN)) |
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#define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM2LPEN)) |
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#define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM3LPEN)) |
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#define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM4LPEN)) |
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#define __HAL_RCC_TIM5_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM5LPEN)) |
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#define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM6LPEN)) |
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#define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM7LPEN)) |
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#define __HAL_RCC_TIM12_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM12LPEN)) |
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#define __HAL_RCC_TIM13_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM13LPEN)) |
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#define __HAL_RCC_TIM14_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM14LPEN)) |
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#define __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_LPTIM1LPEN)) |
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#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) |
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#define __HAL_RCC_CAN3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN3LPEN)) |
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#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ |
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#define __HAL_RCC_SPI2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI2LPEN)) |
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#define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI3LPEN)) |
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#define __HAL_RCC_USART2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART2LPEN)) |
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#define __HAL_RCC_USART3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART3LPEN)) |
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#define __HAL_RCC_UART4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART4LPEN)) |
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#define __HAL_RCC_UART5_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART5LPEN)) |
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#define __HAL_RCC_I2C1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C1LPEN)) |
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#define __HAL_RCC_I2C2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C2LPEN)) |
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#define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C3LPEN)) |
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#define __HAL_RCC_CAN1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN1LPEN)) |
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#define __HAL_RCC_DAC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_DACLPEN)) |
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#define __HAL_RCC_UART7_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART7LPEN)) |
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#define __HAL_RCC_UART8_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART8LPEN)) |
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#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) ||\ |
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defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) ||\ |
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defined (STM32F779xx) || defined (STM32F730xx) |
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#define __HAL_RCC_RTC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_RTCLPEN)) |
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#define __HAL_RCC_RTC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_RTCLPEN)) |
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#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || |
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STM32F769xx || STM32F777xx || STM32F779xx || STM32F730xx */ |
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#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ |
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defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\ |
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defined (STM32F750xx) |
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#define __HAL_RCC_SPDIFRX_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPDIFRXLPEN)) |
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#define __HAL_RCC_I2C4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C4LPEN)) |
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#define __HAL_RCC_CAN2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN2LPEN)) |
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#define __HAL_RCC_CEC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CECLPEN)) |
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#define __HAL_RCC_SPDIFRX_CLK_SLEEP_DISABLE()(RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPDIFRXLPEN)) |
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#define __HAL_RCC_I2C4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C4LPEN)) |
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#define __HAL_RCC_CAN2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN2LPEN)) |
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#define __HAL_RCC_CEC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CECLPEN)) |
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#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ |
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/** @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode. |
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* @note Peripheral clock gating in SLEEP mode can be used to further reduce |
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* power consumption. |
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* @note After wakeup from SLEEP mode, the peripheral clock is enabled again. |
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* @note By default, all peripheral clocks are enabled during SLEEP mode. |
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*/ |
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#define __HAL_RCC_TIM1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM1LPEN)) |
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#define __HAL_RCC_TIM8_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM8LPEN)) |
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#define __HAL_RCC_USART1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_USART1LPEN)) |
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#define __HAL_RCC_USART6_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_USART6LPEN)) |
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#define __HAL_RCC_ADC1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC1LPEN)) |
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#define __HAL_RCC_ADC2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC2LPEN)) |
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#define __HAL_RCC_ADC3_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC3LPEN)) |
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#define __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SDMMC1LPEN)) |
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#define __HAL_RCC_SPI1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI1LPEN)) |
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#define __HAL_RCC_SPI4_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI4LPEN)) |
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#define __HAL_RCC_TIM9_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM9LPEN)) |
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#define __HAL_RCC_TIM10_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM10LPEN)) |
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#define __HAL_RCC_TIM11_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM11LPEN)) |
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#define __HAL_RCC_SPI5_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI5LPEN)) |
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#define __HAL_RCC_SAI1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SAI1LPEN)) |
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#define __HAL_RCC_SAI2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SAI2LPEN)) |
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#if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx) |
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#define __HAL_RCC_LTDC_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_LTDCLPEN)) |
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#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ |
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#define __HAL_RCC_TIM1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM1LPEN)) |
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#define __HAL_RCC_TIM8_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM8LPEN)) |
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#define __HAL_RCC_USART1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_USART1LPEN)) |
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#define __HAL_RCC_USART6_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_USART6LPEN)) |
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#define __HAL_RCC_ADC1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC1LPEN)) |
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#define __HAL_RCC_ADC2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC2LPEN)) |
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#define __HAL_RCC_ADC3_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC3LPEN)) |
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#define __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDMMC1LPEN)) |
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#define __HAL_RCC_SPI1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI1LPEN)) |
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#define __HAL_RCC_SPI4_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI4LPEN)) |
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#define __HAL_RCC_TIM9_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM9LPEN)) |
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#define __HAL_RCC_TIM10_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM10LPEN)) |
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#define __HAL_RCC_TIM11_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM11LPEN)) |
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#define __HAL_RCC_SPI5_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI5LPEN)) |
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#define __HAL_RCC_SAI1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SAI1LPEN)) |
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#define __HAL_RCC_SAI2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SAI2LPEN)) |
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#if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)|| defined (STM32F750xx) |
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#define __HAL_RCC_LTDC_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_LTDCLPEN)) |
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#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ |
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#if defined (STM32F769xx) || defined (STM32F779xx) |
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#define __HAL_RCC_DSI_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_DSILPEN)) |
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#define __HAL_RCC_DSI_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_DSILPEN)) |
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#endif /* STM32F769xx || STM32F779xx */ |
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#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) |
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#define __HAL_RCC_DFSDM1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_DFSDM1LPEN)) |
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#define __HAL_RCC_MDIO_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_MDIOLPEN)) |
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#define __HAL_RCC_DFSDM1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_DFSDM1LPEN)) |
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#define __HAL_RCC_MDIO_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_MDIOLPEN)) |
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#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ |
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#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F765xx) ||\ |
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defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F730xx) |
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#define __HAL_RCC_SDMMC2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SDMMC2LPEN)) |
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#define __HAL_RCC_SDMMC2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDMMC2LPEN)) |
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#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F730xx */ |
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#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ |
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defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\ |
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defined (STM32F750xx) |
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#define __HAL_RCC_SPI6_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI6LPEN)) |
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#define __HAL_RCC_SPI6_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI6LPEN)) |
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#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ |
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/** |
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* @} |
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*/ |
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/** @defgroup RCC_Clock_Sleep_Enable_Disable_Status AHB/APB Peripheral Clock Sleep Enable Disable Status |
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* @brief Get the enable or disable status of the AHB/APB peripheral clock during Low Power (Sleep) mode. |
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* @note Peripheral clock gating in SLEEP mode can be used to further reduce |
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* power consumption. |
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* @note After wakeup from SLEEP mode, the peripheral clock is enabled again. |
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* @note By default, all peripheral clocks are enabled during SLEEP mode. |
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* @{ |
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*/ |
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/** @brief Get the enable or disable status of the AHB1 peripheral clock during Low Power (Sleep) mode. |
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* @note Peripheral clock gating in SLEEP mode can be used to further reduce |
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* power consumption. |
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* @note After wakeup from SLEEP mode, the peripheral clock is enabled again. |
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* @note By default, all peripheral clocks are enabled during SLEEP mode. |
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*/ |
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#define __HAL_RCC_FLITF_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_FLITFLPEN)) != RESET) |
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#define __HAL_RCC_AXI_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_AXILPEN)) != RESET) |
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#define __HAL_RCC_SRAM1_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_SRAM1LPEN)) != RESET) |
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#define __HAL_RCC_SRAM2_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_SRAM2LPEN)) != RESET) |
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#define __HAL_RCC_BKPSRAM_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_BKPSRAMLPEN)) != RESET) |
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#define __HAL_RCC_DTCM_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DTCMLPEN)) != RESET) |
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#define __HAL_RCC_DMA2_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA2LPEN)) != RESET) |
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#define __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_OTGHSLPEN)) != RESET) |
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#define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_OTGHSULPILPEN)) != RESET) |
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#define __HAL_RCC_GPIOA_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOALPEN)) != RESET) |
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#define __HAL_RCC_GPIOB_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOBLPEN)) != RESET) |
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#define __HAL_RCC_GPIOC_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOCLPEN)) != RESET) |
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#define __HAL_RCC_GPIOD_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIODLPEN)) != RESET) |
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#define __HAL_RCC_GPIOE_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOELPEN)) != RESET) |
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#define __HAL_RCC_GPIOF_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOFLPEN)) != RESET) |
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#define __HAL_RCC_GPIOG_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOGLPEN)) != RESET) |
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#define __HAL_RCC_GPIOH_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOHLPEN)) != RESET) |
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#define __HAL_RCC_GPIOI_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOILPEN)) != RESET) |
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#define __HAL_RCC_FLITF_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_FLITFLPEN)) == RESET) |
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#define __HAL_RCC_AXI_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_AXILPEN)) == RESET) |
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#define __HAL_RCC_SRAM1_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_SRAM1LPEN)) == RESET) |
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#define __HAL_RCC_SRAM2_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_SRAM2LPEN)) == RESET) |
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#define __HAL_RCC_BKPSRAM_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_BKPSRAMLPEN)) == RESET) |
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#define __HAL_RCC_DTCM_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DTCMLPEN)) == RESET) |
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#define __HAL_RCC_DMA2_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA2LPEN)) == RESET) |
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#define __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_OTGHSLPEN)) == RESET) |
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#define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_OTGHSULPILPEN)) == RESET) |
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#define __HAL_RCC_GPIOA_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOALPEN)) == RESET) |
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#define __HAL_RCC_GPIOB_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOBLPEN)) == RESET) |
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#define __HAL_RCC_GPIOC_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOCLPEN)) == RESET) |
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#define __HAL_RCC_GPIOD_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIODLPEN)) == RESET) |
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#define __HAL_RCC_GPIOE_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOELPEN)) == RESET) |
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#define __HAL_RCC_GPIOF_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOFLPEN)) == RESET) |
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#define __HAL_RCC_GPIOG_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOGLPEN)) == RESET) |
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#define __HAL_RCC_GPIOH_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOHLPEN)) == RESET) |
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#define __HAL_RCC_GPIOI_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOILPEN)) == RESET) |
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#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ |
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defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\ |
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defined (STM32F750xx) |
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#define __HAL_RCC_DMA2D_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA2DLPEN)) != RESET) |
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#define __HAL_RCC_ETHMAC_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACLPEN)) != RESET) |
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#define __HAL_RCC_ETHMACTX_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACTXLPEN)) != RESET) |
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#define __HAL_RCC_ETHMACRX_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACRXLPEN)) != RESET) |
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#define __HAL_RCC_ETHMACPTP_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACPTPLPEN)) != RESET) |
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#define __HAL_RCC_GPIOJ_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOJLPEN)) != RESET) |
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#define __HAL_RCC_GPIOK_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOKLPEN)) != RESET) |
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#define __HAL_RCC_DMA2D_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA2DLPEN)) == RESET) |
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#define __HAL_RCC_ETHMAC_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACLPEN)) == RESET) |
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#define __HAL_RCC_ETHMACTX_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACTXLPEN)) == RESET) |
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#define __HAL_RCC_ETHMACRX_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACRXLPEN)) == RESET) |
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#define __HAL_RCC_ETHMACPTP_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACPTPLPEN)) == RESET) |
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#define __HAL_RCC_GPIOJ_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOJLPEN)) == RESET) |
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#define __HAL_RCC_GPIOK_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOKLPEN)) == RESET) |
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#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ |
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/** @brief Get the enable or disable status of the AHB2 peripheral clock during Low Power (Sleep) mode. |
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* @note Peripheral clock gating in SLEEP mode can be used to further reduce |
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* power consumption. |
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* @note After wakeup from SLEEP mode, the peripheral clock is enabled again. |
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* @note By default, all peripheral clocks are enabled during SLEEP mode. |
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*/ |
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#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ |
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defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\ |
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defined (STM32F750xx) |
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#define __HAL_RCC_DCMI_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_DCMILPEN)) != RESET) |
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#define __HAL_RCC_DCMI_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_DCMILPEN)) == RESET) |
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#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ |
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#if defined(STM32F767xx) || defined(STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) |
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#define __HAL_RCC_JPEG_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_JPEGLPEN)) != RESET) |
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#define __HAL_RCC_JPEG_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_JPEGLPEN)) == RESET) |
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#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ |
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#define __HAL_RCC_RNG_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_RNGLPEN)) != RESET) |
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#define __HAL_RCC_RNG_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_RNGLPEN)) == RESET) |
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#define __HAL_RCC_USB_OTG_FS_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_OTGFSLPEN)) != RESET) |
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#define __HAL_RCC_USB_OTG_FS_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_OTGFSLPEN)) == RESET) |
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#if defined(STM32F756xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx) |
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#define __HAL_RCC_CRYP_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_CRYPLPEN)) != RESET) |
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#define __HAL_RCC_HASH_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_HASHLPEN)) != RESET) |
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#define __HAL_RCC_CRYP_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_CRYPLPEN)) == RESET) |
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#define __HAL_RCC_HASH_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_HASHLPEN)) == RESET) |
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#endif /* STM32F756xx || STM32F777xx || STM32F779xx || STM32F750xx */ |
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#if defined(STM32F732xx) || defined (STM32F733xx) || defined (STM32F730xx) |
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#define __HAL_RCC_AES_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_AESLPEN)) != RESET) |
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#define __HAL_RCC_AES_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_AESLPEN)) == RESET) |
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#endif /* STM32F732xx || STM32F733xx || STM32F730xx */ |
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/** @brief Get the enable or disable status of the AHB3 peripheral clock during Low Power (Sleep) mode. |
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* @note Peripheral clock gating in SLEEP mode can be used to further reduce |
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* power consumption. |
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* @note After wakeup from SLEEP mode, the peripheral clock is enabled again. |
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* @note By default, all peripheral clocks are enabled during SLEEP mode. |
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*/ |
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#define __HAL_RCC_FMC_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & (RCC_AHB3LPENR_FMCLPEN)) != RESET) |
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#define __HAL_RCC_FMC_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & (RCC_AHB3LPENR_FMCLPEN)) == RESET) |
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#define __HAL_RCC_QSPI_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & (RCC_AHB3LPENR_QSPILPEN)) != RESET) |
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#define __HAL_RCC_QSPI_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & (RCC_AHB3LPENR_QSPILPEN)) == RESET) |
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/** @brief Get the enable or disable status of the APB1 peripheral clock during Low Power (Sleep) mode. |
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* @note Peripheral clock gating in SLEEP mode can be used to further reduce |
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* power consumption. |
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* @note After wakeup from SLEEP mode, the peripheral clock is enabled again. |
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* @note By default, all peripheral clocks are enabled during SLEEP mode. |
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*/ |
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#define __HAL_RCC_TIM2_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM2LPEN)) != RESET) |
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#define __HAL_RCC_TIM3_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM3LPEN)) != RESET) |
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#define __HAL_RCC_TIM4_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM4LPEN)) != RESET) |
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#define __HAL_RCC_TIM5_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM5LPEN)) != RESET) |
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#define __HAL_RCC_TIM6_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM6LPEN)) != RESET) |
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#define __HAL_RCC_TIM7_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM7LPEN)) != RESET) |
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#define __HAL_RCC_TIM12_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM12LPEN)) != RESET) |
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#define __HAL_RCC_TIM13_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM13LPEN)) != RESET) |
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#define __HAL_RCC_TIM14_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM14LPEN)) != RESET) |
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#define __HAL_RCC_LPTIM1_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_LPTIM1LPEN)) != RESET) |
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#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) ||\ |
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defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) ||\ |
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defined (STM32F779xx) || defined (STM32F730xx) |
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#define __HAL_RCC_RTC_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_RTCLPEN)) != RESET) |
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#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || |
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STM32F769xx || STM32F777xx || STM32F779xx || STM32F730xx */ |
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#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) |
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#define __HAL_RCC_CAN3_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_CAN3LPEN)) != RESET) |
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#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ |
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#define __HAL_RCC_SPI2_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_SPI2LPEN)) != RESET) |
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#define __HAL_RCC_SPI3_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_SPI3LPEN)) != RESET) |
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#define __HAL_RCC_USART2_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_USART2LPEN)) != RESET) |
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#define __HAL_RCC_USART3_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_USART3LPEN)) != RESET) |
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#define __HAL_RCC_UART4_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_UART4LPEN)) != RESET) |
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#define __HAL_RCC_UART5_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_UART5LPEN)) != RESET) |
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#define __HAL_RCC_I2C1_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C1LPEN)) != RESET) |
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#define __HAL_RCC_I2C2_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C2LPEN)) != RESET) |
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#define __HAL_RCC_I2C3_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C3LPEN)) != RESET) |
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#define __HAL_RCC_CAN1_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_CAN1LPEN)) != RESET) |
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#define __HAL_RCC_DAC_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_DACLPEN)) != RESET) |
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#define __HAL_RCC_UART7_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_UART7LPEN)) != RESET) |
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#define __HAL_RCC_UART8_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_UART8LPEN)) != RESET) |
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#define __HAL_RCC_TIM2_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM2LPEN)) == RESET) |
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#define __HAL_RCC_TIM3_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM3LPEN)) == RESET) |
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#define __HAL_RCC_TIM4_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM4LPEN)) == RESET) |
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#define __HAL_RCC_TIM5_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM5LPEN)) == RESET) |
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#define __HAL_RCC_TIM6_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM6LPEN)) == RESET) |
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#define __HAL_RCC_TIM7_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM7LPEN)) == RESET) |
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#define __HAL_RCC_TIM12_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM12LPEN)) == RESET) |
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#define __HAL_RCC_TIM13_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM13LPEN)) == RESET) |
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#define __HAL_RCC_TIM14_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM14LPEN)) == RESET) |
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#define __HAL_RCC_LPTIM1_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_LPTIM1LPEN)) == RESET) |
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#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) ||\ |
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defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) ||\ |
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defined (STM32F779xx) || defined (STM32F730xx) |
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#define __HAL_RCC_RTC_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_RTCLPEN)) == RESET) |
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#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || |
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STM32F769xx || STM32F777xx || STM32F779xx || STM32F730xx */ |
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#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) |
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#define __HAL_RCC_CAN3_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_CAN3LPEN)) == RESET) |
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#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ |
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#define __HAL_RCC_SPI2_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_SPI2LPEN)) == RESET) |
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#define __HAL_RCC_SPI3_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_SPI3LPEN)) == RESET) |
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#define __HAL_RCC_USART2_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_USART2LPEN)) == RESET) |
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#define __HAL_RCC_USART3_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_USART3LPEN)) == RESET) |
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#define __HAL_RCC_UART4_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_UART4LPEN)) == RESET) |
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#define __HAL_RCC_UART5_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_UART5LPEN)) == RESET) |
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#define __HAL_RCC_I2C1_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C1LPEN)) == RESET) |
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#define __HAL_RCC_I2C2_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C2LPEN)) == RESET) |
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#define __HAL_RCC_I2C3_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C3LPEN)) == RESET) |
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#define __HAL_RCC_CAN1_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_CAN1LPEN)) == RESET) |
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#define __HAL_RCC_DAC_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_DACLPEN)) == RESET) |
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#define __HAL_RCC_UART7_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_UART7LPEN)) == RESET) |
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#define __HAL_RCC_UART8_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_UART8LPEN)) == RESET) |
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#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ |
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defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\ |
|
defined (STM32F750xx) |
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#define __HAL_RCC_SPDIFRX_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_SPDIFRXLPEN)) != RESET) |
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#define __HAL_RCC_I2C4_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C4LPEN)) != RESET) |
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#define __HAL_RCC_CAN2_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_CAN2LPEN)) != RESET) |
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#define __HAL_RCC_CEC_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_CECLPEN)) != RESET) |
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#define __HAL_RCC_SPDIFRX_IS_CLK_SLEEP_DISABLED()((RCC->APB1LPENR & (RCC_APB1LPENR_SPDIFRXLPEN)) == RESET) |
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#define __HAL_RCC_I2C4_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C4LPEN)) == RESET) |
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#define __HAL_RCC_CAN2_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_CAN2LPEN)) == RESET) |
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#define __HAL_RCC_CEC_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_CECLPEN)) == RESET) |
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#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ |
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/** @brief Get the enable or disable status of the APB2 peripheral clock during Low Power (Sleep) mode. |
|
* @note Peripheral clock gating in SLEEP mode can be used to further reduce |
|
* power consumption. |
|
* @note After wakeup from SLEEP mode, the peripheral clock is enabled again. |
|
* @note By default, all peripheral clocks are enabled during SLEEP mode. |
|
*/ |
|
#define __HAL_RCC_TIM1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM1LPEN)) != RESET) |
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#define __HAL_RCC_TIM8_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM8LPEN)) != RESET) |
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#define __HAL_RCC_USART1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_USART1LPEN)) != RESET) |
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#define __HAL_RCC_USART6_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_USART6LPEN)) != RESET) |
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#define __HAL_RCC_ADC1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_ADC1LPEN)) != RESET) |
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#define __HAL_RCC_ADC2_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_ADC2LPEN)) != RESET) |
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#define __HAL_RCC_ADC3_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_ADC3LPEN)) != RESET) |
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#define __HAL_RCC_SDMMC1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SDMMC1LPEN)) != RESET) |
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#define __HAL_RCC_SPI1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI1LPEN)) != RESET) |
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#define __HAL_RCC_SPI4_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI4LPEN)) != RESET) |
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#define __HAL_RCC_TIM9_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM9LPEN)) != RESET) |
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#define __HAL_RCC_TIM10_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM10LPEN)) != RESET) |
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#define __HAL_RCC_TIM11_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM11LPEN)) != RESET) |
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#define __HAL_RCC_SPI5_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI5LPEN)) != RESET) |
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#define __HAL_RCC_SAI1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI1LPEN)) != RESET) |
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#define __HAL_RCC_SAI2_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI2LPEN)) != RESET) |
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#if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx) |
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#define __HAL_RCC_LTDC_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_LTDCLPEN)) != RESET) |
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#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ |
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#if defined (STM32F769xx) || defined (STM32F779xx) |
|
#define __HAL_RCC_DSI_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_DSILPEN)) != RESET) |
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#endif /* STM32F769xx || STM32F779xx */ |
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#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F765xx) ||\ |
|
defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F730xx) |
|
#define __HAL_RCC_SDMMC2_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SDMMC2LPEN)) != RESET) |
|
#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F730xx */ |
|
#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) |
|
#define __HAL_RCC_DFSDM1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_DFSDM1LPEN)) != RESET) |
|
#define __HAL_RCC_MDIO_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_MDIOLPEN)) != RESET) |
|
#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ |
|
|
|
#define __HAL_RCC_TIM1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM1LPEN)) == RESET) |
|
#define __HAL_RCC_TIM8_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM8LPEN)) == RESET) |
|
#define __HAL_RCC_USART1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_USART1LPEN)) == RESET) |
|
#define __HAL_RCC_USART6_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_USART6LPEN)) == RESET) |
|
#define __HAL_RCC_ADC1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_ADC1LPEN)) == RESET) |
|
#define __HAL_RCC_ADC2_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_ADC2LPEN)) == RESET) |
|
#define __HAL_RCC_ADC3_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_ADC3LPEN)) == RESET) |
|
#define __HAL_RCC_SDMMC1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SDMMC1LPEN)) == RESET) |
|
#define __HAL_RCC_SPI1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI1LPEN)) == RESET) |
|
#define __HAL_RCC_SPI4_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI4LPEN)) == RESET) |
|
#define __HAL_RCC_TIM9_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM9LPEN)) == RESET) |
|
#define __HAL_RCC_TIM10_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM10LPEN)) == RESET) |
|
#define __HAL_RCC_TIM11_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM11LPEN)) == RESET) |
|
#define __HAL_RCC_SPI5_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI5LPEN)) == RESET) |
|
#define __HAL_RCC_SAI1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI1LPEN)) == RESET) |
|
#define __HAL_RCC_SAI2_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI2LPEN)) == RESET) |
|
#if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx) |
|
#define __HAL_RCC_LTDC_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_LTDCLPEN)) == RESET) |
|
#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ |
|
#if defined (STM32F769xx) || defined (STM32F779xx) |
|
#define __HAL_RCC_DSI_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_DSILPEN)) == RESET) |
|
#endif /* STM32F769xx || STM32F779xx */ |
|
#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F765xx) ||\ |
|
defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F730xx) |
|
#define __HAL_RCC_SDMMC2_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SDMMC2LPEN)) == RESET) |
|
#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F730xx */ |
|
#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) |
|
#define __HAL_RCC_DFSDM1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_DFSDM1LPEN)) == RESET) |
|
#define __HAL_RCC_MDIO_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_MDIOLPEN)) == RESET) |
|
#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ |
|
|
|
#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ |
|
defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\ |
|
defined (STM32F750xx) |
|
#define __HAL_RCC_SPI6_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI6LPEN)) != RESET) |
|
#define __HAL_RCC_SPI6_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI6LPEN)) == RESET) |
|
#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ |
|
/** |
|
* @} |
|
*/ |
|
|
|
/*------------------------------- PLL Configuration --------------------------*/ |
|
#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) |
|
/** @brief Macro to configure the main PLL clock source, multiplication and division factors. |
|
* @note This function must be used only when the main PLL is disabled. |
|
* @param __RCC_PLLSource__ specifies the PLL entry clock source. |
|
* This parameter can be one of the following values: |
|
* @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry |
|
* @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry |
|
* @note This clock source (RCC_PLLSource) is common for the main PLL and PLLI2S. |
|
* @param __PLLM__ specifies the division factor for PLL VCO input clock |
|
* This parameter must be a number between Min_Data = 2 and Max_Data = 63. |
|
* @note You have to set the PLLM parameter correctly to ensure that the VCO input |
|
* frequency ranges from 1 to 2 MHz. It is recommended to select a frequency |
|
* of 2 MHz to limit PLL jitter. |
|
* @param __PLLN__ specifies the multiplication factor for PLL VCO output clock |
|
* This parameter must be a number between Min_Data = 50 and Max_Data = 432. |
|
* @note You have to set the PLLN parameter correctly to ensure that the VCO |
|
* output frequency is between 100 and 432 MHz. |
|
* @param __PLLP__ specifies the division factor for main system clock (SYSCLK) |
|
* This parameter must be a number in the range {2, 4, 6, or 8}. |
|
* @note You have to set the PLLP parameter correctly to not exceed 216 MHz on |
|
* the System clock frequency. |
|
* @param __PLLQ__ specifies the division factor for OTG FS, SDMMC and RNG clocks |
|
* This parameter must be a number between Min_Data = 2 and Max_Data = 15. |
|
* @note If the USB OTG FS is used in your application, you have to set the |
|
* PLLQ parameter correctly to have 48 MHz clock for the USB. However, |
|
* the SDMMC and RNG need a frequency lower than or equal to 48 MHz to work |
|
* correctly. |
|
* @param __PLLR__ specifies the division factor for DSI clock |
|
* This parameter must be a number between Min_Data = 2 and Max_Data = 7. |
|
*/ |
|
#define __HAL_RCC_PLL_CONFIG(__RCC_PLLSource__, __PLLM__, __PLLN__, __PLLP__, __PLLQ__,__PLLR__) \ |
|
(RCC->PLLCFGR = ((__RCC_PLLSource__) | (__PLLM__) | \ |
|
((__PLLN__) << RCC_PLLCFGR_PLLN_Pos) | \ |
|
((((__PLLP__) >> 1) -1) << RCC_PLLCFGR_PLLP_Pos) | \ |
|
((__PLLQ__) << RCC_PLLCFGR_PLLQ_Pos) | \ |
|
((__PLLR__) << RCC_PLLCFGR_PLLR_Pos))) |
|
#else |
|
/** @brief Macro to configure the main PLL clock source, multiplication and division factors. |
|
* @note This function must be used only when the main PLL is disabled. |
|
* @param __RCC_PLLSource__ specifies the PLL entry clock source. |
|
* This parameter can be one of the following values: |
|
* @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry |
|
* @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry |
|
* @note This clock source (RCC_PLLSource) is common for the main PLL and PLLI2S. |
|
* @param __PLLM__ specifies the division factor for PLL VCO input clock |
|
* This parameter must be a number between Min_Data = 2 and Max_Data = 63. |
|
* @note You have to set the PLLM parameter correctly to ensure that the VCO input |
|
* frequency ranges from 1 to 2 MHz. It is recommended to select a frequency |
|
* of 2 MHz to limit PLL jitter. |
|
* @param __PLLN__ specifies the multiplication factor for PLL VCO output clock |
|
* This parameter must be a number between Min_Data = 50 and Max_Data = 432. |
|
* @note You have to set the PLLN parameter correctly to ensure that the VCO |
|
* output frequency is between 100 and 432 MHz. |
|
* @param __PLLP__ specifies the division factor for main system clock (SYSCLK) |
|
* This parameter must be a number in the range {2, 4, 6, or 8}. |
|
* @note You have to set the PLLP parameter correctly to not exceed 216 MHz on |
|
* the System clock frequency. |
|
* @param __PLLQ__ specifies the division factor for OTG FS, SDMMC and RNG clocks |
|
* This parameter must be a number between Min_Data = 2 and Max_Data = 15. |
|
* @note If the USB OTG FS is used in your application, you have to set the |
|
* PLLQ parameter correctly to have 48 MHz clock for the USB. However, |
|
* the SDMMC and RNG need a frequency lower than or equal to 48 MHz to work |
|
* correctly. |
|
*/ |
|
#define __HAL_RCC_PLL_CONFIG(__RCC_PLLSource__, __PLLM__, __PLLN__, __PLLP__, __PLLQ__) \ |
|
(RCC->PLLCFGR = (0x20000000 | (__RCC_PLLSource__) | (__PLLM__)| \ |
|
((__PLLN__) << RCC_PLLCFGR_PLLN_Pos) | \ |
|
((((__PLLP__) >> 1) -1) << RCC_PLLCFGR_PLLP_Pos) | \ |
|
((__PLLQ__) << RCC_PLLCFGR_PLLQ_Pos))) |
|
#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ |
|
/*---------------------------------------------------------------------------------------------*/ |
|
|
|
/** @brief Macro to configure the Timers clocks prescalers |
|
* @param __PRESC__ specifies the Timers clocks prescalers selection |
|
* This parameter can be one of the following values: |
|
* @arg RCC_TIMPRES_DESACTIVATED: The Timers kernels clocks prescaler is |
|
* equal to HPRE if PPREx is corresponding to division by 1 or 2, |
|
* else it is equal to [(HPRE * PPREx) / 2] if PPREx is corresponding to |
|
* division by 4 or more. |
|
* @arg RCC_TIMPRES_ACTIVATED: The Timers kernels clocks prescaler is |
|
* equal to HPRE if PPREx is corresponding to division by 1, 2 or 4, |
|
* else it is equal to [(HPRE * PPREx) / 4] if PPREx is corresponding |
|
* to division by 8 or more. |
|
*/ |
|
#define __HAL_RCC_TIMCLKPRESCALER(__PRESC__) do {RCC->DCKCFGR1 &= ~(RCC_DCKCFGR1_TIMPRE);\ |
|
RCC->DCKCFGR1 |= (__PRESC__); \ |
|
}while(0) |
|
|
|
/** @brief Macros to Enable or Disable the PLLISAI. |
|
* @note The PLLSAI is disabled by hardware when entering STOP and STANDBY modes. |
|
*/ |
|
#define __HAL_RCC_PLLSAI_ENABLE() (RCC->CR |= (RCC_CR_PLLSAION)) |
|
#define __HAL_RCC_PLLSAI_DISABLE() (RCC->CR &= ~(RCC_CR_PLLSAION)) |
|
|
|
#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F730xx) |
|
/** @brief Macro to configure the PLLSAI clock multiplication and division factors. |
|
* @note This function must be used only when the PLLSAI is disabled. |
|
* @note PLLSAI clock source is common with the main PLL (configured in |
|
* RCC_PLLConfig function ) |
|
* @param __PLLSAIN__ specifies the multiplication factor for PLLSAI VCO output clock. |
|
* This parameter must be a number between Min_Data = 50 and Max_Data = 432. |
|
* @note You have to set the PLLSAIN parameter correctly to ensure that the VCO |
|
* output frequency is between Min_Data = 100 and Max_Data = 432 MHz. |
|
* @param __PLLSAIP__ specifies the division factor for USB, RNG, SDMMC clocks |
|
* This parameter can be a value of @ref RCCEx_PLLSAIP_Clock_Divider. |
|
* @param __PLLSAIQ__ specifies the division factor for SAI clock |
|
* This parameter must be a number between Min_Data = 2 and Max_Data = 15. |
|
*/ |
|
#define __HAL_RCC_PLLSAI_CONFIG(__PLLSAIN__, __PLLSAIP__, __PLLSAIQ__) \ |
|
(RCC->PLLSAICFGR = ((__PLLSAIN__) << RCC_PLLSAICFGR_PLLSAIN_Pos) |\ |
|
((__PLLSAIP__) << RCC_PLLSAICFGR_PLLSAIP_Pos) |\ |
|
((__PLLSAIQ__) << RCC_PLLSAICFGR_PLLSAIQ_Pos)) |
|
|
|
/** @brief Macro to configure the PLLI2S clock multiplication and division factors. |
|
* @note This macro must be used only when the PLLI2S is disabled. |
|
* @note PLLI2S clock source is common with the main PLL (configured in |
|
* HAL_RCC_ClockConfig() API) |
|
* @param __PLLI2SN__ specifies the multiplication factor for PLLI2S VCO output clock. |
|
* This parameter must be a number between Min_Data = 50 and Max_Data = 432. |
|
* @note You have to set the PLLI2SN parameter correctly to ensure that the VCO |
|
* output frequency is between Min_Data = 100 and Max_Data = 432 MHz. |
|
* @param __PLLI2SQ__ specifies the division factor for SAI clock. |
|
* This parameter must be a number between Min_Data = 2 and Max_Data = 15. |
|
* @param __PLLI2SR__ specifies the division factor for I2S clock |
|
* This parameter must be a number between Min_Data = 2 and Max_Data = 7. |
|
* @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz |
|
* on the I2S clock frequency. |
|
*/ |
|
#define __HAL_RCC_PLLI2S_CONFIG(__PLLI2SN__, __PLLI2SQ__, __PLLI2SR__) \ |
|
(RCC->PLLI2SCFGR = ((__PLLI2SN__) << RCC_PLLI2SCFGR_PLLI2SN_Pos) |\ |
|
((__PLLI2SQ__) << RCC_PLLI2SCFGR_PLLI2SQ_Pos) |\ |
|
((__PLLI2SR__) << RCC_PLLI2SCFGR_PLLI2SR_Pos)) |
|
#else |
|
/** @brief Macro to configure the PLLSAI clock multiplication and division factors. |
|
* @note This function must be used only when the PLLSAI is disabled. |
|
* @note PLLSAI clock source is common with the main PLL (configured in |
|
* RCC_PLLConfig function ) |
|
* @param __PLLSAIN__ specifies the multiplication factor for PLLSAI VCO output clock. |
|
* This parameter must be a number between Min_Data = 50 and Max_Data = 432. |
|
* @note You have to set the PLLSAIN parameter correctly to ensure that the VCO |
|
* output frequency is between Min_Data = 100 and Max_Data = 432 MHz. |
|
* @param __PLLSAIP__ specifies the division factor for USB, RNG, SDMMC clocks |
|
* This parameter can be a value of @ref RCCEx_PLLSAIP_Clock_Divider. |
|
* @param __PLLSAIQ__ specifies the division factor for SAI clock |
|
* This parameter must be a number between Min_Data = 2 and Max_Data = 15. |
|
* @param __PLLSAIR__ specifies the division factor for LTDC clock |
|
* This parameter must be a number between Min_Data = 2 and Max_Data = 7. |
|
*/ |
|
#define __HAL_RCC_PLLSAI_CONFIG(__PLLSAIN__, __PLLSAIP__, __PLLSAIQ__, __PLLSAIR__) \ |
|
(RCC->PLLSAICFGR = ((__PLLSAIN__) << RCC_PLLSAICFGR_PLLSAIN_Pos) |\ |
|
((__PLLSAIP__) << RCC_PLLSAICFGR_PLLSAIP_Pos) |\ |
|
((__PLLSAIQ__) << RCC_PLLSAICFGR_PLLSAIQ_Pos) |\ |
|
((__PLLSAIR__) << RCC_PLLSAICFGR_PLLSAIR_Pos)) |
|
|
|
/** @brief Macro to configure the PLLI2S clock multiplication and division factors. |
|
* @note This macro must be used only when the PLLI2S is disabled. |
|
* @note PLLI2S clock source is common with the main PLL (configured in |
|
* HAL_RCC_ClockConfig() API) |
|
* @param __PLLI2SN__ specifies the multiplication factor for PLLI2S VCO output clock. |
|
* This parameter must be a number between Min_Data = 50 and Max_Data = 432. |
|
* @note You have to set the PLLI2SN parameter correctly to ensure that the VCO |
|
* output frequency is between Min_Data = 100 and Max_Data = 432 MHz. |
|
* @param __PLLI2SP__ specifies the division factor for SPDDIF-RX clock. |
|
* This parameter can be a value of @ref RCCEx_PLLI2SP_Clock_Divider. |
|
* @param __PLLI2SQ__ specifies the division factor for SAI clock. |
|
* This parameter must be a number between Min_Data = 2 and Max_Data = 15. |
|
* @param __PLLI2SR__ specifies the division factor for I2S clock |
|
* This parameter must be a number between Min_Data = 2 and Max_Data = 7. |
|
* @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz |
|
* on the I2S clock frequency. |
|
*/ |
|
#define __HAL_RCC_PLLI2S_CONFIG(__PLLI2SN__, __PLLI2SP__, __PLLI2SQ__, __PLLI2SR__) \ |
|
(RCC->PLLI2SCFGR = ((__PLLI2SN__) << RCC_PLLI2SCFGR_PLLI2SN_Pos) |\ |
|
((__PLLI2SP__) << RCC_PLLI2SCFGR_PLLI2SP_Pos) |\ |
|
((__PLLI2SQ__) << RCC_PLLI2SCFGR_PLLI2SQ_Pos) |\ |
|
((__PLLI2SR__) << RCC_PLLI2SCFGR_PLLI2SR_Pos)) |
|
#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F730xx */ |
|
|
|
/** @brief Macro to configure the SAI clock Divider coming from PLLI2S. |
|
* @note This function must be called before enabling the PLLI2S. |
|
* @param __PLLI2SDivQ__ specifies the PLLI2S division factor for SAI1 clock . |
|
* This parameter must be a number between 1 and 32. |
|
* SAI1 clock frequency = f(PLLI2SQ) / __PLLI2SDivQ__ |
|
*/ |
|
#define __HAL_RCC_PLLI2S_PLLSAICLKDIVQ_CONFIG(__PLLI2SDivQ__) (MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_PLLI2SDIVQ, (__PLLI2SDivQ__)-1)) |
|
|
|
/** @brief Macro to configure the SAI clock Divider coming from PLLSAI. |
|
* @note This function must be called before enabling the PLLSAI. |
|
* @param __PLLSAIDivQ__ specifies the PLLSAI division factor for SAI1 clock . |
|
* This parameter must be a number between Min_Data = 1 and Max_Data = 32. |
|
* SAI1 clock frequency = f(PLLSAIQ) / __PLLSAIDivQ__ |
|
*/ |
|
#define __HAL_RCC_PLLSAI_PLLSAICLKDIVQ_CONFIG(__PLLSAIDivQ__) (MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_PLLSAIDIVQ, ((__PLLSAIDivQ__)-1)<<8)) |
|
|
|
#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ |
|
defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\ |
|
defined (STM32F750xx) |
|
/** @brief Macro to configure the LTDC clock Divider coming from PLLSAI. |
|
* @note This function must be called before enabling the PLLSAI. |
|
* @param __PLLSAIDivR__ specifies the PLLSAI division factor for LTDC clock . |
|
* This parameter can be a value of @ref RCCEx_PLLSAI_DIVR. |
|
* LTDC clock frequency = f(PLLSAIR) / __PLLSAIDivR__ |
|
*/ |
|
#define __HAL_RCC_PLLSAI_PLLSAICLKDIVR_CONFIG(__PLLSAIDivR__)\ |
|
MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_PLLSAIDIVR, (uint32_t)(__PLLSAIDivR__)) |
|
#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ |
|
|
|
/** @brief Macro to configure SAI1 clock source selection. |
|
* @note This function must be called before enabling PLLSAI, PLLI2S and |
|
* the SAI clock. |
|
* @param __SOURCE__ specifies the SAI1 clock source. |
|
* This parameter can be one of the following values: |
|
* @arg RCC_SAI1CLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used |
|
* as SAI1 clock. |
|
* @arg RCC_SAI1CLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used |
|
* as SAI1 clock. |
|
* @arg RCC_SAI1CLKSOURCE_PIN: External clock mapped on the I2S_CKIN pin |
|
* used as SAI1 clock. |
|
* @arg RCC_SAI1CLKSOURCE_PLLSRC: HSI or HSE depending from PLL Source clock |
|
* used as SAI1 clock. |
|
* @note The RCC_SAI1CLKSOURCE_PLLSRC value is only available with STM32F767/769/777/779xx Devices |
|
*/ |
|
#define __HAL_RCC_SAI1_CONFIG(__SOURCE__)\ |
|
MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_SAI1SEL, (uint32_t)(__SOURCE__)) |
|
|
|
/** @brief Macro to get the SAI1 clock source. |
|
* @retval The clock source can be one of the following values: |
|
* @arg RCC_SAI1CLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used |
|
* as SAI1 clock. |
|
* @arg RCC_SAI1CLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used |
|
* as SAI1 clock. |
|
* @arg RCC_SAI1CLKSOURCE_PIN: External clock mapped on the I2S_CKIN pin |
|
* used as SAI1 clock. |
|
* @arg RCC_SAI1CLKSOURCE_PLLSRC: HSI or HSE depending from PLL Source clock |
|
* used as SAI1 clock. |
|
* @note The RCC_SAI1CLKSOURCE_PLLSRC value is only available with STM32F767/769/777/779xx Devices |
|
*/ |
|
#define __HAL_RCC_GET_SAI1_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR1, RCC_DCKCFGR1_SAI1SEL))) |
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/** @brief Macro to configure SAI2 clock source selection. |
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* @note This function must be called before enabling PLLSAI, PLLI2S and |
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* the SAI clock. |
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* @param __SOURCE__ specifies the SAI2 clock source. |
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* This parameter can be one of the following values: |
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* @arg RCC_SAI2CLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used |
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* as SAI2 clock. |
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* @arg RCC_SAI2CLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used |
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* as SAI2 clock. |
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* @arg RCC_SAI2CLKSOURCE_PIN: External clock mapped on the I2S_CKIN pin |
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* used as SAI2 clock. |
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* @arg RCC_SAI2CLKSOURCE_PLLSRC: HSI or HSE depending from PLL Source clock |
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* used as SAI2 clock. |
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* @note The RCC_SAI2CLKSOURCE_PLLSRC value is only available with STM32F767/769/777/779xx Devices |
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*/ |
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#define __HAL_RCC_SAI2_CONFIG(__SOURCE__)\ |
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MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_SAI2SEL, (uint32_t)(__SOURCE__)) |
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/** @brief Macro to get the SAI2 clock source. |
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* @retval The clock source can be one of the following values: |
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* @arg RCC_SAI2CLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used |
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* as SAI2 clock. |
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* @arg RCC_SAI2CLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used |
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* as SAI2 clock. |
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* @arg RCC_SAI2CLKSOURCE_PIN: External clock mapped on the I2S_CKIN pin |
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* used as SAI2 clock. |
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* @arg RCC_SAI2CLKSOURCE_PLLSRC: HSI or HSE depending from PLL Source clock |
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* used as SAI2 clock. |
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* @note The RCC_SAI2CLKSOURCE_PLLSRC value is only available with STM32F767/769/777/779xx Devices |
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*/ |
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#define __HAL_RCC_GET_SAI2_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR1, RCC_DCKCFGR1_SAI2SEL))) |
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/** @brief Enable PLLSAI_RDY interrupt. |
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*/ |
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#define __HAL_RCC_PLLSAI_ENABLE_IT() (RCC->CIR |= (RCC_CIR_PLLSAIRDYIE)) |
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/** @brief Disable PLLSAI_RDY interrupt. |
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*/ |
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#define __HAL_RCC_PLLSAI_DISABLE_IT() (RCC->CIR &= ~(RCC_CIR_PLLSAIRDYIE)) |
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/** @brief Clear the PLLSAI RDY interrupt pending bits. |
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*/ |
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#define __HAL_RCC_PLLSAI_CLEAR_IT() (RCC->CIR |= (RCC_CIR_PLLSAIRDYF)) |
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/** @brief Check the PLLSAI RDY interrupt has occurred or not. |
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* @retval The new state (TRUE or FALSE). |
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*/ |
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#define __HAL_RCC_PLLSAI_GET_IT() ((RCC->CIR & (RCC_CIR_PLLSAIRDYIE)) == (RCC_CIR_PLLSAIRDYIE)) |
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/** @brief Check PLLSAI RDY flag is set or not. |
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* @retval The new state (TRUE or FALSE). |
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*/ |
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#define __HAL_RCC_PLLSAI_GET_FLAG() ((RCC->CR & (RCC_CR_PLLSAIRDY)) == (RCC_CR_PLLSAIRDY)) |
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/** @brief Macro to Get I2S clock source selection. |
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* @retval The clock source can be one of the following values: |
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* @arg RCC_I2SCLKSOURCE_PLLI2S: PLLI2S VCO output clock divided by PLLI2SR used as I2S clock. |
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* @arg RCC_I2SCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as I2S clock source |
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*/ |
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#define __HAL_RCC_GET_I2SCLKSOURCE() (READ_BIT(RCC->CFGR, RCC_CFGR_I2SSRC)) |
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/** @brief Macro to configure the I2C1 clock (I2C1CLK). |
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* |
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* @param __I2C1_CLKSOURCE__ specifies the I2C1 clock source. |
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* This parameter can be one of the following values: |
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* @arg RCC_I2C1CLKSOURCE_PCLK1: PCLK1 selected as I2C1 clock |
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* @arg RCC_I2C1CLKSOURCE_HSI: HSI selected as I2C1 clock |
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* @arg RCC_I2C1CLKSOURCE_SYSCLK: System Clock selected as I2C1 clock |
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*/ |
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#define __HAL_RCC_I2C1_CONFIG(__I2C1_CLKSOURCE__) \ |
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MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C1SEL, (uint32_t)(__I2C1_CLKSOURCE__)) |
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/** @brief Macro to get the I2C1 clock source. |
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* @retval The clock source can be one of the following values: |
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* @arg RCC_I2C1CLKSOURCE_PCLK1: PCLK1 selected as I2C1 clock |
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* @arg RCC_I2C1CLKSOURCE_HSI: HSI selected as I2C1 clock |
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* @arg RCC_I2C1CLKSOURCE_SYSCLK: System Clock selected as I2C1 clock |
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*/ |
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#define __HAL_RCC_GET_I2C1_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C1SEL))) |
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/** @brief Macro to configure the I2C2 clock (I2C2CLK). |
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* |
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* @param __I2C2_CLKSOURCE__ specifies the I2C2 clock source. |
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* This parameter can be one of the following values: |
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* @arg RCC_I2C2CLKSOURCE_PCLK1: PCLK1 selected as I2C2 clock |
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* @arg RCC_I2C2CLKSOURCE_HSI: HSI selected as I2C2 clock |
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* @arg RCC_I2C2CLKSOURCE_SYSCLK: System Clock selected as I2C2 clock |
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*/ |
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#define __HAL_RCC_I2C2_CONFIG(__I2C2_CLKSOURCE__) \ |
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MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C2SEL, (uint32_t)(__I2C2_CLKSOURCE__)) |
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/** @brief Macro to get the I2C2 clock source. |
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* @retval The clock source can be one of the following values: |
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* @arg RCC_I2C2CLKSOURCE_PCLK1: PCLK1 selected as I2C2 clock |
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* @arg RCC_I2C2CLKSOURCE_HSI: HSI selected as I2C2 clock |
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* @arg RCC_I2C2CLKSOURCE_SYSCLK: System Clock selected as I2C2 clock |
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*/ |
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#define __HAL_RCC_GET_I2C2_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C2SEL))) |
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/** @brief Macro to configure the I2C3 clock (I2C3CLK). |
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* |
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* @param __I2C3_CLKSOURCE__ specifies the I2C3 clock source. |
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* This parameter can be one of the following values: |
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* @arg RCC_I2C3CLKSOURCE_PCLK1: PCLK1 selected as I2C3 clock |
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* @arg RCC_I2C3CLKSOURCE_HSI: HSI selected as I2C3 clock |
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* @arg RCC_I2C3CLKSOURCE_SYSCLK: System Clock selected as I2C3 clock |
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*/ |
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#define __HAL_RCC_I2C3_CONFIG(__I2C3_CLKSOURCE__) \ |
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MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C3SEL, (uint32_t)(__I2C3_CLKSOURCE__)) |
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/** @brief macro to get the I2C3 clock source. |
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* @retval The clock source can be one of the following values: |
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* @arg RCC_I2C3CLKSOURCE_PCLK1: PCLK1 selected as I2C3 clock |
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* @arg RCC_I2C3CLKSOURCE_HSI: HSI selected as I2C3 clock |
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* @arg RCC_I2C3CLKSOURCE_SYSCLK: System Clock selected as I2C3 clock |
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*/ |
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#define __HAL_RCC_GET_I2C3_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C3SEL))) |
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/** @brief Macro to configure the I2C4 clock (I2C4CLK). |
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* |
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* @param __I2C4_CLKSOURCE__ specifies the I2C4 clock source. |
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* This parameter can be one of the following values: |
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* @arg RCC_I2C4CLKSOURCE_PCLK1: PCLK1 selected as I2C4 clock |
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* @arg RCC_I2C4CLKSOURCE_HSI: HSI selected as I2C4 clock |
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* @arg RCC_I2C4CLKSOURCE_SYSCLK: System Clock selected as I2C4 clock |
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*/ |
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#define __HAL_RCC_I2C4_CONFIG(__I2C4_CLKSOURCE__) \ |
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MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C4SEL, (uint32_t)(__I2C4_CLKSOURCE__)) |
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/** @brief macro to get the I2C4 clock source. |
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* @retval The clock source can be one of the following values: |
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* @arg RCC_I2C4CLKSOURCE_PCLK1: PCLK1 selected as I2C4 clock |
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* @arg RCC_I2C4CLKSOURCE_HSI: HSI selected as I2C4 clock |
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* @arg RCC_I2C4CLKSOURCE_SYSCLK: System Clock selected as I2C4 clock |
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*/ |
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#define __HAL_RCC_GET_I2C4_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C4SEL))) |
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/** @brief Macro to configure the USART1 clock (USART1CLK). |
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* |
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* @param __USART1_CLKSOURCE__ specifies the USART1 clock source. |
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* This parameter can be one of the following values: |
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* @arg RCC_USART1CLKSOURCE_PCLK2: PCLK2 selected as USART1 clock |
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* @arg RCC_USART1CLKSOURCE_HSI: HSI selected as USART1 clock |
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* @arg RCC_USART1CLKSOURCE_SYSCLK: System Clock selected as USART1 clock |
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* @arg RCC_USART1CLKSOURCE_LSE: LSE selected as USART1 clock |
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*/ |
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#define __HAL_RCC_USART1_CONFIG(__USART1_CLKSOURCE__) \ |
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MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_USART1SEL, (uint32_t)(__USART1_CLKSOURCE__)) |
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/** @brief macro to get the USART1 clock source. |
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* @retval The clock source can be one of the following values: |
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* @arg RCC_USART1CLKSOURCE_PCLK2: PCLK2 selected as USART1 clock |
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* @arg RCC_USART1CLKSOURCE_HSI: HSI selected as USART1 clock |
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* @arg RCC_USART1CLKSOURCE_SYSCLK: System Clock selected as USART1 clock |
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* @arg RCC_USART1CLKSOURCE_LSE: LSE selected as USART1 clock |
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*/ |
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#define __HAL_RCC_GET_USART1_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_USART1SEL))) |
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/** @brief Macro to configure the USART2 clock (USART2CLK). |
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* |
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* @param __USART2_CLKSOURCE__ specifies the USART2 clock source. |
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* This parameter can be one of the following values: |
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* @arg RCC_USART2CLKSOURCE_PCLK1: PCLK1 selected as USART2 clock |
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* @arg RCC_USART2CLKSOURCE_HSI: HSI selected as USART2 clock |
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* @arg RCC_USART2CLKSOURCE_SYSCLK: System Clock selected as USART2 clock |
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* @arg RCC_USART2CLKSOURCE_LSE: LSE selected as USART2 clock |
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*/ |
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#define __HAL_RCC_USART2_CONFIG(__USART2_CLKSOURCE__) \ |
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MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_USART2SEL, (uint32_t)(__USART2_CLKSOURCE__)) |
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/** @brief macro to get the USART2 clock source. |
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* @retval The clock source can be one of the following values: |
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* @arg RCC_USART2CLKSOURCE_PCLK1: PCLK1 selected as USART2 clock |
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* @arg RCC_USART2CLKSOURCE_HSI: HSI selected as USART2 clock |
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* @arg RCC_USART2CLKSOURCE_SYSCLK: System Clock selected as USART2 clock |
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* @arg RCC_USART2CLKSOURCE_LSE: LSE selected as USART2 clock |
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*/ |
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#define __HAL_RCC_GET_USART2_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_USART2SEL))) |
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/** @brief Macro to configure the USART3 clock (USART3CLK). |
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* |
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* @param __USART3_CLKSOURCE__ specifies the USART3 clock source. |
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* This parameter can be one of the following values: |
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* @arg RCC_USART3CLKSOURCE_PCLK1: PCLK1 selected as USART3 clock |
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* @arg RCC_USART3CLKSOURCE_HSI: HSI selected as USART3 clock |
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* @arg RCC_USART3CLKSOURCE_SYSCLK: System Clock selected as USART3 clock |
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* @arg RCC_USART3CLKSOURCE_LSE: LSE selected as USART3 clock |
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*/ |
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#define __HAL_RCC_USART3_CONFIG(__USART3_CLKSOURCE__) \ |
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MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_USART3SEL, (uint32_t)(__USART3_CLKSOURCE__)) |
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/** @brief macro to get the USART3 clock source. |
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* @retval The clock source can be one of the following values: |
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* @arg RCC_USART3CLKSOURCE_PCLK1: PCLK1 selected as USART3 clock |
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* @arg RCC_USART3CLKSOURCE_HSI: HSI selected as USART3 clock |
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* @arg RCC_USART3CLKSOURCE_SYSCLK: System Clock selected as USART3 clock |
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* @arg RCC_USART3CLKSOURCE_LSE: LSE selected as USART3 clock |
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*/ |
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#define __HAL_RCC_GET_USART3_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_USART3SEL))) |
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/** @brief Macro to configure the UART4 clock (UART4CLK). |
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* |
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* @param __UART4_CLKSOURCE__ specifies the UART4 clock source. |
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* This parameter can be one of the following values: |
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* @arg RCC_UART4CLKSOURCE_PCLK1: PCLK1 selected as UART4 clock |
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* @arg RCC_UART4CLKSOURCE_HSI: HSI selected as UART4 clock |
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* @arg RCC_UART4CLKSOURCE_SYSCLK: System Clock selected as UART4 clock |
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* @arg RCC_UART4CLKSOURCE_LSE: LSE selected as UART4 clock |
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*/ |
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#define __HAL_RCC_UART4_CONFIG(__UART4_CLKSOURCE__) \ |
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MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_UART4SEL, (uint32_t)(__UART4_CLKSOURCE__)) |
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/** @brief macro to get the UART4 clock source. |
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* @retval The clock source can be one of the following values: |
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* @arg RCC_UART4CLKSOURCE_PCLK1: PCLK1 selected as UART4 clock |
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* @arg RCC_UART4CLKSOURCE_HSI: HSI selected as UART4 clock |
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* @arg RCC_UART4CLKSOURCE_SYSCLK: System Clock selected as UART4 clock |
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* @arg RCC_UART4CLKSOURCE_LSE: LSE selected as UART4 clock |
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*/ |
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#define __HAL_RCC_GET_UART4_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_UART4SEL))) |
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/** @brief Macro to configure the UART5 clock (UART5CLK). |
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* |
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* @param __UART5_CLKSOURCE__ specifies the UART5 clock source. |
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* This parameter can be one of the following values: |
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* @arg RCC_UART5CLKSOURCE_PCLK1: PCLK1 selected as UART5 clock |
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* @arg RCC_UART5CLKSOURCE_HSI: HSI selected as UART5 clock |
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* @arg RCC_UART5CLKSOURCE_SYSCLK: System Clock selected as UART5 clock |
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* @arg RCC_UART5CLKSOURCE_LSE: LSE selected as UART5 clock |
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*/ |
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#define __HAL_RCC_UART5_CONFIG(__UART5_CLKSOURCE__) \ |
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MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_UART5SEL, (uint32_t)(__UART5_CLKSOURCE__)) |
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/** @brief macro to get the UART5 clock source. |
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* @retval The clock source can be one of the following values: |
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* @arg RCC_UART5CLKSOURCE_PCLK1: PCLK1 selected as UART5 clock |
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* @arg RCC_UART5CLKSOURCE_HSI: HSI selected as UART5 clock |
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* @arg RCC_UART5CLKSOURCE_SYSCLK: System Clock selected as UART5 clock |
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* @arg RCC_UART5CLKSOURCE_LSE: LSE selected as UART5 clock |
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*/ |
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#define __HAL_RCC_GET_UART5_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_UART5SEL))) |
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/** @brief Macro to configure the USART6 clock (USART6CLK). |
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* |
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* @param __USART6_CLKSOURCE__ specifies the USART6 clock source. |
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* This parameter can be one of the following values: |
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* @arg RCC_USART6CLKSOURCE_PCLK1: PCLK1 selected as USART6 clock |
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* @arg RCC_USART6CLKSOURCE_HSI: HSI selected as USART6 clock |
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* @arg RCC_USART6CLKSOURCE_SYSCLK: System Clock selected as USART6 clock |
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* @arg RCC_USART6CLKSOURCE_LSE: LSE selected as USART6 clock |
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*/ |
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#define __HAL_RCC_USART6_CONFIG(__USART6_CLKSOURCE__) \ |
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MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_USART6SEL, (uint32_t)(__USART6_CLKSOURCE__)) |
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/** @brief macro to get the USART6 clock source. |
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* @retval The clock source can be one of the following values: |
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* @arg RCC_USART6CLKSOURCE_PCLK1: PCLK1 selected as USART6 clock |
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* @arg RCC_USART6CLKSOURCE_HSI: HSI selected as USART6 clock |
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* @arg RCC_USART6CLKSOURCE_SYSCLK: System Clock selected as USART6 clock |
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* @arg RCC_USART6CLKSOURCE_LSE: LSE selected as USART6 clock |
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*/ |
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#define __HAL_RCC_GET_USART6_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_USART6SEL))) |
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/** @brief Macro to configure the UART7 clock (UART7CLK). |
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* |
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* @param __UART7_CLKSOURCE__ specifies the UART7 clock source. |
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* This parameter can be one of the following values: |
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* @arg RCC_UART7CLKSOURCE_PCLK1: PCLK1 selected as UART7 clock |
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* @arg RCC_UART7CLKSOURCE_HSI: HSI selected as UART7 clock |
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* @arg RCC_UART7CLKSOURCE_SYSCLK: System Clock selected as UART7 clock |
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* @arg RCC_UART7CLKSOURCE_LSE: LSE selected as UART7 clock |
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*/ |
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#define __HAL_RCC_UART7_CONFIG(__UART7_CLKSOURCE__) \ |
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MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_UART7SEL, (uint32_t)(__UART7_CLKSOURCE__)) |
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/** @brief macro to get the UART7 clock source. |
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* @retval The clock source can be one of the following values: |
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* @arg RCC_UART7CLKSOURCE_PCLK1: PCLK1 selected as UART7 clock |
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* @arg RCC_UART7CLKSOURCE_HSI: HSI selected as UART7 clock |
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* @arg RCC_UART7CLKSOURCE_SYSCLK: System Clock selected as UART7 clock |
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* @arg RCC_UART7CLKSOURCE_LSE: LSE selected as UART7 clock |
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*/ |
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#define __HAL_RCC_GET_UART7_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_UART7SEL))) |
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/** @brief Macro to configure the UART8 clock (UART8CLK). |
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* |
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* @param __UART8_CLKSOURCE__ specifies the UART8 clock source. |
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* This parameter can be one of the following values: |
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* @arg RCC_UART8CLKSOURCE_PCLK1: PCLK1 selected as UART8 clock |
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* @arg RCC_UART8CLKSOURCE_HSI: HSI selected as UART8 clock |
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* @arg RCC_UART8CLKSOURCE_SYSCLK: System Clock selected as UART8 clock |
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* @arg RCC_UART8CLKSOURCE_LSE: LSE selected as UART8 clock |
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*/ |
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#define __HAL_RCC_UART8_CONFIG(__UART8_CLKSOURCE__) \ |
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MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_UART8SEL, (uint32_t)(__UART8_CLKSOURCE__)) |
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/** @brief macro to get the UART8 clock source. |
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* @retval The clock source can be one of the following values: |
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* @arg RCC_UART8CLKSOURCE_PCLK1: PCLK1 selected as UART8 clock |
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* @arg RCC_UART8CLKSOURCE_HSI: HSI selected as UART8 clock |
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* @arg RCC_UART8CLKSOURCE_SYSCLK: System Clock selected as UART8 clock |
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* @arg RCC_UART8CLKSOURCE_LSE: LSE selected as UART8 clock |
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*/ |
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#define __HAL_RCC_GET_UART8_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_UART8SEL))) |
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/** @brief Macro to configure the LPTIM1 clock (LPTIM1CLK). |
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* |
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* @param __LPTIM1_CLKSOURCE__ specifies the LPTIM1 clock source. |
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* This parameter can be one of the following values: |
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* @arg RCC_LPTIM1CLKSOURCE_PCLK1: PCLK selected as LPTIM1 clock |
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* @arg RCC_LPTIM1CLKSOURCE_HSI: HSI selected as LPTIM1 clock |
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* @arg RCC_LPTIM1CLKSOURCE_LSI: LSI selected as LPTIM1 clock |
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* @arg RCC_LPTIM1CLKSOURCE_LSE: LSE selected as LPTIM1 clock |
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*/ |
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#define __HAL_RCC_LPTIM1_CONFIG(__LPTIM1_CLKSOURCE__) \ |
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MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_LPTIM1SEL, (uint32_t)(__LPTIM1_CLKSOURCE__)) |
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/** @brief macro to get the LPTIM1 clock source. |
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* @retval The clock source can be one of the following values: |
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* @arg RCC_LPTIM1CLKSOURCE_PCLK1: PCLK selected as LPTIM1 clock |
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* @arg RCC_LPTIM1CLKSOURCE_HSI: HSI selected as LPTIM1 clock |
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* @arg RCC_LPTIM1CLKSOURCE_LSI: LSI selected as LPTIM1 clock |
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* @arg RCC_LPTIM1CLKSOURCE_LSE: LSE selected as LPTIM1 clock |
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*/ |
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#define __HAL_RCC_GET_LPTIM1_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_LPTIM1SEL))) |
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/** @brief Macro to configure the CEC clock (CECCLK). |
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* |
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* @param __CEC_CLKSOURCE__ specifies the CEC clock source. |
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* This parameter can be one of the following values: |
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* @arg RCC_CECCLKSOURCE_LSE: LSE selected as CEC clock |
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* @arg RCC_CECCLKSOURCE_HSI: HSI divided by 488 selected as CEC clock |
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*/ |
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#define __HAL_RCC_CEC_CONFIG(__CEC_CLKSOURCE__) \ |
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MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CECSEL, (uint32_t)(__CEC_CLKSOURCE__)) |
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/** @brief macro to get the CEC clock source. |
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* @retval The clock source can be one of the following values: |
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* @arg RCC_CECCLKSOURCE_LSE: LSE selected as CEC clock |
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* @arg RCC_CECCLKSOURCE_HSI: HSI selected as CEC clock |
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*/ |
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#define __HAL_RCC_GET_CEC_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_CECSEL))) |
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/** @brief Macro to configure the CLK48 source (CLK48CLK). |
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* |
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* @param __CLK48_SOURCE__ specifies the CLK48 clock source. |
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* This parameter can be one of the following values: |
|
* @arg RCC_CLK48SOURCE_PLL: PLL selected as CLK48 source |
|
* @arg RCC_CLK48SOURCE_PLLSAIP: PLLSAIP selected as CLK48 source |
|
*/ |
|
#define __HAL_RCC_CLK48_CONFIG(__CLK48_SOURCE__) \ |
|
MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL, (uint32_t)(__CLK48_SOURCE__)) |
|
|
|
/** @brief macro to get the CLK48 source. |
|
* @retval The clock source can be one of the following values: |
|
* @arg RCC_CLK48SOURCE_PLL: PLL used as CLK48 source |
|
* @arg RCC_CLK48SOURCE_PLLSAIP: PLLSAIP used as CLK48 source |
|
*/ |
|
#define __HAL_RCC_GET_CLK48_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL))) |
|
|
|
/** @brief Macro to configure the SDMMC1 clock (SDMMC1CLK). |
|
* |
|
* @param __SDMMC1_CLKSOURCE__ specifies the SDMMC1 clock source. |
|
* This parameter can be one of the following values: |
|
* @arg RCC_SDMMC1CLKSOURCE_CLK48: CLK48 selected as SDMMC clock |
|
* @arg RCC_SDMMC1CLKSOURCE_SYSCLK: SYSCLK selected as SDMMC clock |
|
*/ |
|
#define __HAL_RCC_SDMMC1_CONFIG(__SDMMC1_CLKSOURCE__) \ |
|
MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_SDMMC1SEL, (uint32_t)(__SDMMC1_CLKSOURCE__)) |
|
|
|
/** @brief macro to get the SDMMC1 clock source. |
|
* @retval The clock source can be one of the following values: |
|
* @arg RCC_SDMMC1CLKSOURCE_CLK48: CLK48 selected as SDMMC1 clock |
|
* @arg RCC_SDMMC1CLKSOURCE_SYSCLK: SYSCLK selected as SDMMC1 clock |
|
*/ |
|
#define __HAL_RCC_GET_SDMMC1_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_SDMMC1SEL))) |
|
|
|
#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F765xx) ||\ |
|
defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F730xx) |
|
/** @brief Macro to configure the SDMMC2 clock (SDMMC2CLK). |
|
* @param __SDMMC2_CLKSOURCE__ specifies the SDMMC2 clock source. |
|
* This parameter can be one of the following values: |
|
* @arg RCC_SDMMC2CLKSOURCE_CLK48: CLK48 selected as SDMMC2 clock |
|
* @arg RCC_SDMMC2CLKSOURCE_SYSCLK: SYSCLK selected as SDMMC2 clock |
|
*/ |
|
#define __HAL_RCC_SDMMC2_CONFIG(__SDMMC2_CLKSOURCE__) \ |
|
MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_SDMMC2SEL, (uint32_t)(__SDMMC2_CLKSOURCE__)) |
|
|
|
/** @brief macro to get the SDMMC2 clock source. |
|
* @retval The clock source can be one of the following values: |
|
* @arg RCC_SDMMC2CLKSOURCE_CLK48: CLK48 selected as SDMMC2 clock |
|
* @arg RCC_SDMMC2CLKSOURCE_SYSCLK: SYSCLK selected as SDMMC2 clock |
|
*/ |
|
#define __HAL_RCC_GET_SDMMC2_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_SDMMC2SEL))) |
|
#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F730xx */ |
|
|
|
#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) |
|
/** @brief Macro to configure the DFSDM1 clock |
|
* @param __DFSDM1_CLKSOURCE__ specifies the DFSDM1 clock source. |
|
* This parameter can be one of the following values: |
|
* @arg RCC_DFSDM1CLKSOURCE_PCLK2: PCLK2 Clock selected as DFSDM clock |
|
* @arg RCC_DFSDMCLKSOURCE_SYSCLK: System Clock selected as DFSDM clock |
|
*/ |
|
#define __HAL_RCC_DFSDM1_CONFIG(__DFSDM1_CLKSOURCE__) \ |
|
MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_DFSDM1SEL, (uint32_t)(__DFSDM1_CLKSOURCE__)) |
|
|
|
/** @brief Macro to get the DFSDM1 clock source. |
|
* @retval The clock source can be one of the following values: |
|
* @arg RCC_DFSDM1CLKSOURCE_PCLK2: PCLK2 Clock selected as DFSDM1 clock |
|
* @arg RCC_DFSDM1CLKSOURCE_SYSCLK: System Clock selected as DFSDM1 clock |
|
*/ |
|
#define __HAL_RCC_GET_DFSDM1_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR1, RCC_DCKCFGR1_DFSDM1SEL))) |
|
|
|
/** @brief Macro to configure the DFSDM1 Audio clock |
|
* @param __DFSDM1AUDIO_CLKSOURCE__ specifies the DFSDM1 Audio clock source. |
|
* This parameter can be one of the following values: |
|
* @arg RCC_DFSDM1AUDIOCLKSOURCE_SAI1: SAI1 Clock selected as DFSDM1 Audio clock |
|
* @arg RCC_DFSDM1AUDIOCLKSOURCE_SAI2: SAI2 Clock selected as DFSDM1 Audio clock |
|
*/ |
|
#define __HAL_RCC_DFSDM1AUDIO_CONFIG(__DFSDM1AUDIO_CLKSOURCE__) \ |
|
MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_ADFSDM1SEL, (uint32_t)(__DFSDM1AUDIO_CLKSOURCE__)) |
|
|
|
/** @brief Macro to get the DFSDM1 Audio clock source. |
|
* @retval The clock source can be one of the following values: |
|
* @arg RCC_DFSDM1AUDIOCLKSOURCE_SAI1: SAI1 Clock selected as DFSDM1 Audio clock |
|
* @arg RCC_DFSDM1AUDIOCLKSOURCE_SAI2: SAI2 Clock selected as DFSDM1 Audio clock |
|
*/ |
|
#define __HAL_RCC_GET_DFSDM1AUDIO_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR1, RCC_DCKCFGR1_ADFSDM1SEL))) |
|
#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ |
|
|
|
#if defined (STM32F769xx) || defined (STM32F779xx) |
|
/** @brief Macro to configure the DSI clock. |
|
* @param __DSI_CLKSOURCE__ specifies the DSI clock source. |
|
* This parameter can be one of the following values: |
|
* @arg RCC_DSICLKSOURCE_PLLR: PLLR output used as DSI clock. |
|
* @arg RCC_DSICLKSOURCE_DSIPHY: DSI-PHY output used as DSI clock. |
|
*/ |
|
#define __HAL_RCC_DSI_CONFIG(__DSI_CLKSOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_DSISEL, (uint32_t)(__DSI_CLKSOURCE__))) |
|
|
|
/** @brief Macro to Get the DSI clock. |
|
* @retval The clock source can be one of the following values: |
|
* @arg RCC_DSICLKSOURCE_PLLR: PLLR output used as DSI clock. |
|
* @arg RCC_DSICLKSOURCE_DSIPHY: DSI-PHY output used as DSI clock. |
|
*/ |
|
#define __HAL_RCC_GET_DSI_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_DSISEL)) |
|
#endif /* STM32F769xx || STM32F779xx */ |
|
/** |
|
* @} |
|
*/ |
|
|
|
/* Exported functions --------------------------------------------------------*/ |
|
/** @addtogroup RCCEx_Exported_Functions_Group1 |
|
* @{ |
|
*/ |
|
HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit); |
|
void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit); |
|
uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk); |
|
HAL_StatusTypeDef HAL_RCCEx_EnablePLLI2S(RCC_PLLI2SInitTypeDef *PLLI2SInit); |
|
HAL_StatusTypeDef HAL_RCCEx_DisablePLLI2S(void); |
|
HAL_StatusTypeDef HAL_RCCEx_EnablePLLSAI(RCC_PLLSAIInitTypeDef *PLLSAIInit); |
|
HAL_StatusTypeDef HAL_RCCEx_DisablePLLSAI(void); |
|
/** |
|
* @} |
|
*/ |
|
/* Private macros ------------------------------------------------------------*/ |
|
/** @addtogroup RCCEx_Private_Macros RCCEx Private Macros |
|
* @{ |
|
*/ |
|
/** @defgroup RCCEx_IS_RCC_Definitions RCC Private macros to check input parameters |
|
* @{ |
|
*/ |
|
#if defined(STM32F756xx) || defined(STM32F746xx) || defined(STM32F750xx) |
|
#define IS_RCC_PERIPHCLOCK(SELECTION) \ |
|
((((SELECTION) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) || \ |
|
(((SELECTION) & RCC_PERIPHCLK_LTDC) == RCC_PERIPHCLK_LTDC) || \ |
|
(((SELECTION) & RCC_PERIPHCLK_TIM) == RCC_PERIPHCLK_TIM) || \ |
|
(((SELECTION) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \ |
|
(((SELECTION) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \ |
|
(((SELECTION) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || \ |
|
(((SELECTION) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) || \ |
|
(((SELECTION) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5) || \ |
|
(((SELECTION) & RCC_PERIPHCLK_USART6) == RCC_PERIPHCLK_USART6) || \ |
|
(((SELECTION) & RCC_PERIPHCLK_UART7) == RCC_PERIPHCLK_UART7) || \ |
|
(((SELECTION) & RCC_PERIPHCLK_UART8) == RCC_PERIPHCLK_UART8) || \ |
|
(((SELECTION) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \ |
|
(((SELECTION) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \ |
|
(((SELECTION) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \ |
|
(((SELECTION) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4) || \ |
|
(((SELECTION) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \ |
|
(((SELECTION) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) || \ |
|
(((SELECTION) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) || \ |
|
(((SELECTION) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48) || \ |
|
(((SELECTION) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC) || \ |
|
(((SELECTION) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1) || \ |
|
(((SELECTION) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX) || \ |
|
(((SELECTION) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)) |
|
#elif defined(STM32F745xx) |
|
#define IS_RCC_PERIPHCLOCK(SELECTION) \ |
|
((((SELECTION) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) || \ |
|
(((SELECTION) & RCC_PERIPHCLK_TIM) == RCC_PERIPHCLK_TIM) || \ |
|
(((SELECTION) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \ |
|
(((SELECTION) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \ |
|
(((SELECTION) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || \ |
|
(((SELECTION) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) || \ |
|
(((SELECTION) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5) || \ |
|
(((SELECTION) & RCC_PERIPHCLK_USART6) == RCC_PERIPHCLK_USART6) || \ |
|
(((SELECTION) & RCC_PERIPHCLK_UART7) == RCC_PERIPHCLK_UART7) || \ |
|
(((SELECTION) & RCC_PERIPHCLK_UART8) == RCC_PERIPHCLK_UART8) || \ |
|
(((SELECTION) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \ |
|
(((SELECTION) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \ |
|
(((SELECTION) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \ |
|
(((SELECTION) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4) || \ |
|
(((SELECTION) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \ |
|
(((SELECTION) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) || \ |
|
(((SELECTION) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) || \ |
|
(((SELECTION) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48) || \ |
|
(((SELECTION) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC) || \ |
|
(((SELECTION) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1) || \ |
|
(((SELECTION) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX) || \ |
|
(((SELECTION) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)) |
|
#elif defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) |
|
#define IS_RCC_PERIPHCLOCK(SELECTION) \ |
|
((((SELECTION) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) || \ |
|
(((SELECTION) & RCC_PERIPHCLK_LTDC) == RCC_PERIPHCLK_LTDC) || \ |
|
(((SELECTION) & RCC_PERIPHCLK_TIM) == RCC_PERIPHCLK_TIM) || \ |
|
(((SELECTION) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \ |
|
(((SELECTION) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \ |
|
(((SELECTION) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || \ |
|
(((SELECTION) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) || \ |
|
(((SELECTION) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5) || \ |
|
(((SELECTION) & RCC_PERIPHCLK_USART6) == RCC_PERIPHCLK_USART6) || \ |
|
(((SELECTION) & RCC_PERIPHCLK_UART7) == RCC_PERIPHCLK_UART7) || \ |
|
(((SELECTION) & RCC_PERIPHCLK_UART8) == RCC_PERIPHCLK_UART8) || \ |
|
(((SELECTION) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \ |
|
(((SELECTION) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \ |
|
(((SELECTION) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \ |
|
(((SELECTION) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4) || \ |
|
(((SELECTION) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \ |
|
(((SELECTION) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) || \ |
|
(((SELECTION) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) || \ |
|
(((SELECTION) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48) || \ |
|
(((SELECTION) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC) || \ |
|
(((SELECTION) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1) || \ |
|
(((SELECTION) & RCC_PERIPHCLK_SDMMC2) == RCC_PERIPHCLK_SDMMC2) || \ |
|
(((SELECTION) & RCC_PERIPHCLK_DFSDM1) == RCC_PERIPHCLK_DFSDM1) || \ |
|
(((SELECTION) & RCC_PERIPHCLK_DFSDM1_AUDIO) == RCC_PERIPHCLK_DFSDM1_AUDIO) || \ |
|
(((SELECTION) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX) || \ |
|
(((SELECTION) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)) |
|
#elif defined (STM32F765xx) |
|
#define IS_RCC_PERIPHCLOCK(SELECTION) \ |
|
((((SELECTION) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) || \ |
|
(((SELECTION) & RCC_PERIPHCLK_TIM) == RCC_PERIPHCLK_TIM) || \ |
|
(((SELECTION) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \ |
|
(((SELECTION) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \ |
|
(((SELECTION) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || \ |
|
(((SELECTION) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) || \ |
|
(((SELECTION) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5) || \ |
|
(((SELECTION) & RCC_PERIPHCLK_USART6) == RCC_PERIPHCLK_USART6) || \ |
|
(((SELECTION) & RCC_PERIPHCLK_UART7) == RCC_PERIPHCLK_UART7) || \ |
|
(((SELECTION) & RCC_PERIPHCLK_UART8) == RCC_PERIPHCLK_UART8) || \ |
|
(((SELECTION) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \ |
|
(((SELECTION) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \ |
|
(((SELECTION) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \ |
|
(((SELECTION) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4) || \ |
|
(((SELECTION) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \ |
|
(((SELECTION) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) || \ |
|
(((SELECTION) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) || \ |
|
(((SELECTION) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48) || \ |
|
(((SELECTION) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC) || \ |
|
(((SELECTION) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1) || \ |
|
(((SELECTION) & RCC_PERIPHCLK_SDMMC2) == RCC_PERIPHCLK_SDMMC2) || \ |
|
(((SELECTION) & RCC_PERIPHCLK_DFSDM1) == RCC_PERIPHCLK_DFSDM1) || \ |
|
(((SELECTION) & RCC_PERIPHCLK_DFSDM1_AUDIO) == RCC_PERIPHCLK_DFSDM1_AUDIO) || \ |
|
(((SELECTION) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX) || \ |
|
(((SELECTION) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)) |
|
#elif defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F730xx) |
|
#define IS_RCC_PERIPHCLOCK(SELECTION) \ |
|
((((SELECTION) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) || \ |
|
(((SELECTION) & RCC_PERIPHCLK_TIM) == RCC_PERIPHCLK_TIM) || \ |
|
(((SELECTION) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \ |
|
(((SELECTION) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \ |
|
(((SELECTION) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || \ |
|
(((SELECTION) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) || \ |
|
(((SELECTION) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5) || \ |
|
(((SELECTION) & RCC_PERIPHCLK_USART6) == RCC_PERIPHCLK_USART6) || \ |
|
(((SELECTION) & RCC_PERIPHCLK_UART7) == RCC_PERIPHCLK_UART7) || \ |
|
(((SELECTION) & RCC_PERIPHCLK_UART8) == RCC_PERIPHCLK_UART8) || \ |
|
(((SELECTION) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \ |
|
(((SELECTION) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \ |
|
(((SELECTION) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \ |
|
(((SELECTION) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \ |
|
(((SELECTION) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) || \ |
|
(((SELECTION) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) || \ |
|
(((SELECTION) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48) || \ |
|
(((SELECTION) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1) || \ |
|
(((SELECTION) & RCC_PERIPHCLK_SDMMC2) == RCC_PERIPHCLK_SDMMC2) || \ |
|
(((SELECTION) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)) |
|
#endif /* STM32F746xx || STM32F756xx || STM32F750xx */ |
|
#define IS_RCC_PLLI2SN_VALUE(VALUE) ((50 <= (VALUE)) && ((VALUE) <= 432)) |
|
#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) || defined (STM32F767xx) || \ |
|
defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx) |
|
#define IS_RCC_PLLI2SP_VALUE(VALUE) (((VALUE) == RCC_PLLI2SP_DIV2) ||\ |
|
((VALUE) == RCC_PLLI2SP_DIV4) ||\ |
|
((VALUE) == RCC_PLLI2SP_DIV6) ||\ |
|
((VALUE) == RCC_PLLI2SP_DIV8)) |
|
#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ |
|
#define IS_RCC_PLLI2SQ_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 15)) |
|
#define IS_RCC_PLLI2SR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7)) |
|
|
|
#define IS_RCC_PLLSAIN_VALUE(VALUE) ((50 <= (VALUE)) && ((VALUE) <= 432)) |
|
#define IS_RCC_PLLSAIP_VALUE(VALUE) (((VALUE) == RCC_PLLSAIP_DIV2) ||\ |
|
((VALUE) == RCC_PLLSAIP_DIV4) ||\ |
|
((VALUE) == RCC_PLLSAIP_DIV6) ||\ |
|
((VALUE) == RCC_PLLSAIP_DIV8)) |
|
#define IS_RCC_PLLSAIQ_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 15)) |
|
#define IS_RCC_PLLSAIR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7)) |
|
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#define IS_RCC_PLLSAI_DIVQ_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 32)) |
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#define IS_RCC_PLLI2S_DIVQ_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 32)) |
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#define IS_RCC_PLLSAI_DIVR_VALUE(VALUE) (((VALUE) == RCC_PLLSAIDIVR_2) ||\ |
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((VALUE) == RCC_PLLSAIDIVR_4) ||\ |
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((VALUE) == RCC_PLLSAIDIVR_8) ||\ |
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((VALUE) == RCC_PLLSAIDIVR_16)) |
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#define IS_RCC_I2SCLKSOURCE(SOURCE) (((SOURCE) == RCC_I2SCLKSOURCE_PLLI2S) || \ |
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((SOURCE) == RCC_I2SCLKSOURCE_EXT)) |
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#define IS_RCC_SDMMC1CLKSOURCE(SOURCE) (((SOURCE) == RCC_SDMMC1CLKSOURCE_SYSCLK) || \ |
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((SOURCE) == RCC_SDMMC1CLKSOURCE_CLK48)) |
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#define IS_RCC_CECCLKSOURCE(SOURCE) (((SOURCE) == RCC_CECCLKSOURCE_HSI) || \ |
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((SOURCE) == RCC_CECCLKSOURCE_LSE)) |
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#define IS_RCC_USART1CLKSOURCE(SOURCE) \ |
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(((SOURCE) == RCC_USART1CLKSOURCE_PCLK2) || \ |
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((SOURCE) == RCC_USART1CLKSOURCE_SYSCLK) || \ |
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((SOURCE) == RCC_USART1CLKSOURCE_LSE) || \ |
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((SOURCE) == RCC_USART1CLKSOURCE_HSI)) |
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#define IS_RCC_USART2CLKSOURCE(SOURCE) \ |
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(((SOURCE) == RCC_USART2CLKSOURCE_PCLK1) || \ |
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((SOURCE) == RCC_USART2CLKSOURCE_SYSCLK) || \ |
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((SOURCE) == RCC_USART2CLKSOURCE_LSE) || \ |
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((SOURCE) == RCC_USART2CLKSOURCE_HSI)) |
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#define IS_RCC_USART3CLKSOURCE(SOURCE) \ |
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(((SOURCE) == RCC_USART3CLKSOURCE_PCLK1) || \ |
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((SOURCE) == RCC_USART3CLKSOURCE_SYSCLK) || \ |
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((SOURCE) == RCC_USART3CLKSOURCE_LSE) || \ |
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((SOURCE) == RCC_USART3CLKSOURCE_HSI)) |
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#define IS_RCC_UART4CLKSOURCE(SOURCE) \ |
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(((SOURCE) == RCC_UART4CLKSOURCE_PCLK1) || \ |
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((SOURCE) == RCC_UART4CLKSOURCE_SYSCLK) || \ |
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((SOURCE) == RCC_UART4CLKSOURCE_LSE) || \ |
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((SOURCE) == RCC_UART4CLKSOURCE_HSI)) |
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#define IS_RCC_UART5CLKSOURCE(SOURCE) \ |
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(((SOURCE) == RCC_UART5CLKSOURCE_PCLK1) || \ |
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((SOURCE) == RCC_UART5CLKSOURCE_SYSCLK) || \ |
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((SOURCE) == RCC_UART5CLKSOURCE_LSE) || \ |
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((SOURCE) == RCC_UART5CLKSOURCE_HSI)) |
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#define IS_RCC_USART6CLKSOURCE(SOURCE) \ |
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(((SOURCE) == RCC_USART6CLKSOURCE_PCLK2) || \ |
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((SOURCE) == RCC_USART6CLKSOURCE_SYSCLK) || \ |
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((SOURCE) == RCC_USART6CLKSOURCE_LSE) || \ |
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((SOURCE) == RCC_USART6CLKSOURCE_HSI)) |
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#define IS_RCC_UART7CLKSOURCE(SOURCE) \ |
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(((SOURCE) == RCC_UART7CLKSOURCE_PCLK1) || \ |
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((SOURCE) == RCC_UART7CLKSOURCE_SYSCLK) || \ |
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((SOURCE) == RCC_UART7CLKSOURCE_LSE) || \ |
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((SOURCE) == RCC_UART7CLKSOURCE_HSI)) |
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#define IS_RCC_UART8CLKSOURCE(SOURCE) \ |
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(((SOURCE) == RCC_UART8CLKSOURCE_PCLK1) || \ |
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((SOURCE) == RCC_UART8CLKSOURCE_SYSCLK) || \ |
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((SOURCE) == RCC_UART8CLKSOURCE_LSE) || \ |
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((SOURCE) == RCC_UART8CLKSOURCE_HSI)) |
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#define IS_RCC_I2C1CLKSOURCE(SOURCE) \ |
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(((SOURCE) == RCC_I2C1CLKSOURCE_PCLK1) || \ |
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((SOURCE) == RCC_I2C1CLKSOURCE_SYSCLK)|| \ |
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((SOURCE) == RCC_I2C1CLKSOURCE_HSI)) |
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#define IS_RCC_I2C2CLKSOURCE(SOURCE) \ |
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(((SOURCE) == RCC_I2C2CLKSOURCE_PCLK1) || \ |
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((SOURCE) == RCC_I2C2CLKSOURCE_SYSCLK)|| \ |
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((SOURCE) == RCC_I2C2CLKSOURCE_HSI)) |
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#define IS_RCC_I2C3CLKSOURCE(SOURCE) \ |
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(((SOURCE) == RCC_I2C3CLKSOURCE_PCLK1) || \ |
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((SOURCE) == RCC_I2C3CLKSOURCE_SYSCLK)|| \ |
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((SOURCE) == RCC_I2C3CLKSOURCE_HSI)) |
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#define IS_RCC_I2C4CLKSOURCE(SOURCE) \ |
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(((SOURCE) == RCC_I2C4CLKSOURCE_PCLK1) || \ |
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((SOURCE) == RCC_I2C4CLKSOURCE_SYSCLK)|| \ |
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((SOURCE) == RCC_I2C4CLKSOURCE_HSI)) |
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#define IS_RCC_LPTIM1CLK(SOURCE) \ |
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(((SOURCE) == RCC_LPTIM1CLKSOURCE_PCLK1) || \ |
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((SOURCE) == RCC_LPTIM1CLKSOURCE_LSI) || \ |
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((SOURCE) == RCC_LPTIM1CLKSOURCE_HSI) || \ |
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((SOURCE) == RCC_LPTIM1CLKSOURCE_LSE)) |
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#define IS_RCC_CLK48SOURCE(SOURCE) \ |
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(((SOURCE) == RCC_CLK48SOURCE_PLLSAIP) || \ |
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((SOURCE) == RCC_CLK48SOURCE_PLL)) |
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#define IS_RCC_TIMPRES(VALUE) \ |
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(((VALUE) == RCC_TIMPRES_DESACTIVATED) || \ |
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((VALUE) == RCC_TIMPRES_ACTIVATED)) |
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#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F745xx) ||\ |
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defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F730xx) || defined (STM32F750xx) |
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#define IS_RCC_SAI1CLKSOURCE(SOURCE) (((SOURCE) == RCC_SAI1CLKSOURCE_PLLSAI) || \ |
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((SOURCE) == RCC_SAI1CLKSOURCE_PLLI2S) || \ |
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((SOURCE) == RCC_SAI1CLKSOURCE_PIN)) |
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#define IS_RCC_SAI2CLKSOURCE(SOURCE) (((SOURCE) == RCC_SAI2CLKSOURCE_PLLSAI) || \ |
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((SOURCE) == RCC_SAI2CLKSOURCE_PLLI2S) || \ |
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((SOURCE) == RCC_SAI2CLKSOURCE_PIN)) |
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#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F745xx || STM32F746xx || STM32F756xx || STM32F750xx || STM32F730xx */ |
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#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) |
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#define IS_RCC_PLLR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7)) |
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#define IS_RCC_SAI1CLKSOURCE(SOURCE) (((SOURCE) == RCC_SAI1CLKSOURCE_PLLSAI) || \ |
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((SOURCE) == RCC_SAI1CLKSOURCE_PLLI2S) || \ |
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((SOURCE) == RCC_SAI1CLKSOURCE_PIN) || \ |
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((SOURCE) == RCC_SAI1CLKSOURCE_PLLSRC)) |
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#define IS_RCC_SAI2CLKSOURCE(SOURCE) (((SOURCE) == RCC_SAI2CLKSOURCE_PLLSAI) || \ |
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((SOURCE) == RCC_SAI2CLKSOURCE_PLLI2S) || \ |
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((SOURCE) == RCC_SAI2CLKSOURCE_PIN) || \ |
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((SOURCE) == RCC_SAI2CLKSOURCE_PLLSRC)) |
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#define IS_RCC_DFSDM1CLKSOURCE(SOURCE) (((SOURCE) == RCC_DFSDM1CLKSOURCE_PCLK2) || \ |
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((SOURCE) == RCC_DFSDM1CLKSOURCE_SYSCLK)) |
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#define IS_RCC_DFSDM1AUDIOCLKSOURCE(SOURCE) (((SOURCE) == RCC_DFSDM1AUDIOCLKSOURCE_SAI1) || \ |
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((SOURCE) == RCC_DFSDM1AUDIOCLKSOURCE_SAI2)) |
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#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ |
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#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F765xx) ||\ |
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defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F730xx) |
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#define IS_RCC_SDMMC2CLKSOURCE(SOURCE) (((SOURCE) == RCC_SDMMC2CLKSOURCE_SYSCLK) || \ |
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((SOURCE) == RCC_SDMMC2CLKSOURCE_CLK48)) |
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#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F730xx */ |
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#if defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) |
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#define IS_RCC_DSIBYTELANECLKSOURCE(SOURCE) (((SOURCE) == RCC_DSICLKSOURCE_PLLR) ||\ |
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((SOURCE) == RCC_DSICLKSOURCE_DSIPHY)) |
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#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ |
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/** |
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* @} |
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*/ |
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/** |
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* @} |
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*/ |
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/** |
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* @} |
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*/ |
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/** |
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* @} |
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*/ |
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#ifdef __cplusplus |
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} |
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#endif |
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#endif /* __STM32F7xx_HAL_RCC_EX_H */ |
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/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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