From 63a6ff14f366afec12e058e73acf65768d0caa21 Mon Sep 17 00:00:00 2001 From: Goran Mahovlic Date: Thu, 18 Aug 2022 17:11:27 +0200 Subject: [PATCH] Adding BPS Components --- .../BSP/Components/mfxstm32l152/Release_Notes.html | 133 ++ Drivers/BSP/Components/mfxstm32l152/mfxstm32l152.c | 1586 ++++++++++++++++++++ Drivers/BSP/Components/mfxstm32l152/mfxstm32l152.h | 650 ++++++++ 3 files changed, 2369 insertions(+) create mode 100644 Drivers/BSP/Components/mfxstm32l152/Release_Notes.html create mode 100644 Drivers/BSP/Components/mfxstm32l152/mfxstm32l152.c create mode 100644 Drivers/BSP/Components/mfxstm32l152/mfxstm32l152.h diff --git a/Drivers/BSP/Components/mfxstm32l152/Release_Notes.html b/Drivers/BSP/Components/mfxstm32l152/Release_Notes.html new file mode 100644 index 0000000..c212854 --- /dev/null +++ b/Drivers/BSP/Components/mfxstm32l152/Release_Notes.html @@ -0,0 +1,133 @@ + + + + + + + Release Notes for MFXSTM32L152 Component Drivers + + + + + + +
+
+
+

Release Notes for

+

MFXSTM32L152 Component Drivers

+

Copyright © 2015 STMicroelectronics
+

+ +
+

License

+

Licensed by ST under BSD 3-Clause license (the "License"). You may not use this package except in compliance with the License. You may obtain a copy of the License at:

+

https://opensource.org/licenses/BSD-3-Clause

+

Purpose

+

This directory contains the MFXSTM32L152 component drivers.

+
+
+

Update History

+
+ +
+

Main Changes

+
    +
  • Remove useless assignment in mfxstm32l152_GetInstance() and mfxstm32l152_ReleaseInstance() functions
    • +
+
+
+
+ +
+

Main Changes

+
    +
  • Update release notes format
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+
+
+
+ +
+

Main Changes

+
    +
  • Reformat the BSD 3-Clause license declaration in the files header (replace license terms by a web reference to OSI website where those terms lie)
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+
+
+
+ +
+

Main Changes

+
    +
  • Update comments to be used for PDSC generation
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+
+
+
+ +
+

Main Changes

+
    +
  • Add Shunt management of MFXSTM32L152 component +
      +
    • new mfxstm32l152_IDD_ConfigShuntNbLimit() and mfxstm32l152_IDD_GetShuntUsed() APIs
      • +
    • +
  • Add mfxstm32l152_WriteReg() API
    • +
+

NOTE This release must be used with BSP Common driver V4.0.0 or later

+
+
+
+ +
+

Main Changes

+
    +
  • mfxstm32l152_IO_Config(): remove unnecessary delay
    • +
  • mfxstm32l152_TS_DetectTouch(): improve TouchScreen speed
    • +
  • mfxstm32l152_IDD_Config(): add configuration of number of measure to be performed, with delay between 2 measures
    • +
+

NOTE
+This release must be used with BSP Common driver V3.0.0 or later

+
+
+
+ +
+

Main Changes

+
    +
  • Low Power management of MFXSTM32L152 component: +
      +
    • New mfxstm32l152_DeInit() and mfxstm32l152_WakeUp() API
      • +
    • mfxstm32l152_LowPower() API completed to be MFXSTM32L152 in Standby mode
      • +
    • +
+

NOTE
+This release must be used with BSP Common driver V2.2.0 or later

+
+
+
+ +
+

Main Changes

+
    +
  • First official release of MFXSTM32L152 IO Expander component driver.
    • +
+

NOTE
+This release must be used with BSP Common driver V2.1.0 or later

+
+
+
+
+ + + diff --git a/Drivers/BSP/Components/mfxstm32l152/mfxstm32l152.c b/Drivers/BSP/Components/mfxstm32l152/mfxstm32l152.c new file mode 100644 index 0000000..df6c1ef --- /dev/null +++ b/Drivers/BSP/Components/mfxstm32l152/mfxstm32l152.c @@ -0,0 +1,1586 @@ +/** + ****************************************************************************** + * @file mfxstm32l152.c + * @author MCD Application Team + * @brief This file provides a set of functions needed to manage the MFXSTM32L152 + * IO Expander devices. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2015 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "mfxstm32l152.h" + +/** @addtogroup BSP + * @{ + */ + +/** @addtogroup Component + * @{ + */ + +/** @defgroup MFXSTM32L152 + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ + +/** @defgroup MFXSTM32L152_Private_Types_Definitions + * @{ + */ + +/* Private define ------------------------------------------------------------*/ + +/** @defgroup MFXSTM32L152_Private_Defines + * @{ + */ +#define MFXSTM32L152_MAX_INSTANCE 3 + +/* Private macro -------------------------------------------------------------*/ + +/** @defgroup MFXSTM32L152_Private_Macros + * @{ + */ + +/* Private variables ---------------------------------------------------------*/ + +/** @defgroup MFXSTM32L152_Private_Variables + * @{ + */ + +/* Touch screen driver structure initialization */ +TS_DrvTypeDef mfxstm32l152_ts_drv = +{ + mfxstm32l152_Init, + mfxstm32l152_ReadID, + mfxstm32l152_Reset, + + mfxstm32l152_TS_Start, + mfxstm32l152_TS_DetectTouch, + mfxstm32l152_TS_GetXY, + + mfxstm32l152_TS_EnableIT, + mfxstm32l152_TS_ClearIT, + mfxstm32l152_TS_ITStatus, + mfxstm32l152_TS_DisableIT, +}; + +/* IO driver structure initialization */ +IO_DrvTypeDef mfxstm32l152_io_drv = +{ + mfxstm32l152_Init, + mfxstm32l152_ReadID, + mfxstm32l152_Reset, + + mfxstm32l152_IO_Start, + mfxstm32l152_IO_Config, + mfxstm32l152_IO_WritePin, + mfxstm32l152_IO_ReadPin, + + mfxstm32l152_IO_EnableIT, + mfxstm32l152_IO_DisableIT, + mfxstm32l152_IO_ITStatus, + mfxstm32l152_IO_ClearIT, +}; + +/* IDD driver structure initialization */ +IDD_DrvTypeDef mfxstm32l152_idd_drv = +{ + mfxstm32l152_Init, + mfxstm32l152_DeInit, + mfxstm32l152_ReadID, + mfxstm32l152_Reset, + mfxstm32l152_LowPower, + mfxstm32l152_WakeUp, + + mfxstm32l152_IDD_Start, + mfxstm32l152_IDD_Config, + mfxstm32l152_IDD_GetValue, + + mfxstm32l152_IDD_EnableIT, + mfxstm32l152_IDD_ClearIT, + mfxstm32l152_IDD_GetITStatus, + mfxstm32l152_IDD_DisableIT, + + mfxstm32l152_Error_EnableIT, + mfxstm32l152_Error_ClearIT, + mfxstm32l152_Error_GetITStatus, + mfxstm32l152_Error_DisableIT, + mfxstm32l152_Error_ReadSrc, + mfxstm32l152_Error_ReadMsg +}; + + +/* mfxstm32l152 instances by address */ +uint8_t mfxstm32l152[MFXSTM32L152_MAX_INSTANCE] = {0}; +/** + * @} + */ + +/* Private function prototypes -----------------------------------------------*/ + +/** @defgroup MFXSTM32L152_Private_Function_Prototypes + * @{ + */ +static uint8_t mfxstm32l152_GetInstance(uint16_t DeviceAddr); +static uint8_t mfxstm32l152_ReleaseInstance(uint16_t DeviceAddr); +static void mfxstm32l152_reg24_setPinValue(uint16_t DeviceAddr, uint8_t RegisterAddr, uint32_t PinPosition, uint8_t PinValue ); + +/* Private functions ---------------------------------------------------------*/ + +/** @defgroup MFXSTM32L152_Private_Functions + * @{ + */ + +/** + * @brief Initialize the mfxstm32l152 and configure the needed hardware resources + * @param DeviceAddr: Device address on communication Bus. + * @retval None + */ +void mfxstm32l152_Init(uint16_t DeviceAddr) +{ + uint8_t instance; + uint8_t empty; + + /* Check if device instance already exists */ + instance = mfxstm32l152_GetInstance(DeviceAddr); + + /* To prevent double initialization */ + if(instance == 0xFF) + { + /* Look for empty instance */ + empty = mfxstm32l152_GetInstance(0); + + if(empty < MFXSTM32L152_MAX_INSTANCE) + { + /* Register the current device instance */ + mfxstm32l152[empty] = DeviceAddr; + + /* Initialize IO BUS layer */ + MFX_IO_Init(); + } + } + + mfxstm32l152_SetIrqOutPinPolarity(DeviceAddr, MFXSTM32L152_OUT_PIN_POLARITY_HIGH); + mfxstm32l152_SetIrqOutPinType(DeviceAddr, MFXSTM32L152_OUT_PIN_TYPE_PUSHPULL); +} + +/** + * @brief DeInitialize the mfxstm32l152 and unconfigure the needed hardware resources + * @param DeviceAddr: Device address on communication Bus. + * @retval None + */ +void mfxstm32l152_DeInit(uint16_t DeviceAddr) +{ + uint8_t instance; + + /* release existing instance */ + instance = mfxstm32l152_ReleaseInstance(DeviceAddr); + + /* De-Init only if instance was previously registered */ + if(instance != 0xFF) + { + /* De-Initialize IO BUS layer */ + MFX_IO_DeInit(); + } +} + +/** + * @brief Reset the mfxstm32l152 by Software. + * @param DeviceAddr: Device address on communication Bus. + * @retval None + */ +void mfxstm32l152_Reset(uint16_t DeviceAddr) +{ + /* Soft Reset */ + MFX_IO_Write(DeviceAddr, MFXSTM32L152_REG_ADR_SYS_CTRL, MFXSTM32L152_SWRST); + + /* Wait for a delay to ensure registers erasing */ + MFX_IO_Delay(10); +} + +/** + * @brief Put mfxstm32l152 Device in Low Power standby mode + * @param DeviceAddr: Device address on communication Bus. + * @retval None + */ +void mfxstm32l152_LowPower(uint16_t DeviceAddr) +{ + /* Enter standby mode */ + MFX_IO_Write(DeviceAddr, MFXSTM32L152_REG_ADR_SYS_CTRL, MFXSTM32L152_STANDBY); + + /* enable wakeup pin */ + MFX_IO_EnableWakeupPin(); +} + +/** + * @brief WakeUp mfxstm32l152 from standby mode + * @param DeviceAddr: Device address on communication Bus. + * @retval None + */ +void mfxstm32l152_WakeUp(uint16_t DeviceAddr) +{ + uint8_t instance; + + /* Check if device instance already exists */ + instance = mfxstm32l152_GetInstance(DeviceAddr); + + /* if instance does not exist, first initialize pins*/ + if(instance == 0xFF) + { + /* enable wakeup pin */ + MFX_IO_EnableWakeupPin(); + } + + /* toggle wakeup pin */ + MFX_IO_Wakeup(); +} + +/** + * @brief Read the MFXSTM32L152 IO Expander device ID. + * @param DeviceAddr: Device address on communication Bus. + * @retval The Device ID (two bytes). + */ +uint16_t mfxstm32l152_ReadID(uint16_t DeviceAddr) +{ + uint8_t id; + + /* Wait for a delay to ensure the state of registers */ + MFX_IO_Delay(1); + + /* Initialize IO BUS layer */ + MFX_IO_Init(); + + id = MFX_IO_Read(DeviceAddr, MFXSTM32L152_REG_ADR_ID); + + /* Return the device ID value */ + return (id); +} + +/** + * @brief Read the MFXSTM32L152 device firmware version. + * @param DeviceAddr: Device address on communication Bus. + * @retval The Device FW version (two bytes). + */ +uint16_t mfxstm32l152_ReadFwVersion(uint16_t DeviceAddr) +{ + uint8_t data[2]; + + MFX_IO_ReadMultiple((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_FW_VERSION_MSB, data, sizeof(data)) ; + + /* Recompose MFX firmware value */ + return ((data[0] << 8) | data[1]); +} + +/** + * @brief Enable the interrupt mode for the selected IT source + * @param DeviceAddr: Device address on communication Bus. + * @param Source: The interrupt source to be configured, could be: + * @arg MFXSTM32L152_IRQ_GPIO: IO interrupt + * @arg MFXSTM32L152_IRQ_IDD : IDD interrupt + * @arg MFXSTM32L152_IRQ_ERROR : Error interrupt + * @arg MFXSTM32L152_IRQ_TS_DET : Touch Screen Controller Touch Detected interrupt + * @arg MFXSTM32L152_IRQ_TS_NE : Touch Screen FIFO Not Empty + * @arg MFXSTM32L152_IRQ_TS_TH : Touch Screen FIFO threshold triggered + * @arg MFXSTM32L152_IRQ_TS_FULL : Touch Screen FIFO Full + * @arg MFXSTM32L152_IRQ_TS_OVF : Touch Screen FIFO Overflow + * @retval None + */ +void mfxstm32l152_EnableITSource(uint16_t DeviceAddr, uint8_t Source) +{ + uint8_t tmp = 0; + + /* Get the current value of the INT_EN register */ + tmp = MFX_IO_Read(DeviceAddr, MFXSTM32L152_REG_ADR_IRQ_SRC_EN); + + /* Set the interrupts to be Enabled */ + tmp |= Source; + + /* Set the register */ + MFX_IO_Write(DeviceAddr, MFXSTM32L152_REG_ADR_IRQ_SRC_EN, tmp); +} + +/** + * @brief Disable the interrupt mode for the selected IT source + * @param DeviceAddr: Device address on communication Bus. + * @param Source: The interrupt source to be configured, could be: + * @arg MFXSTM32L152_IRQ_GPIO: IO interrupt + * @arg MFXSTM32L152_IRQ_IDD : IDD interrupt + * @arg MFXSTM32L152_IRQ_ERROR : Error interrupt + * @arg MFXSTM32L152_IRQ_TS_DET : Touch Screen Controller Touch Detected interrupt + * @arg MFXSTM32L152_IRQ_TS_NE : Touch Screen FIFO Not Empty + * @arg MFXSTM32L152_IRQ_TS_TH : Touch Screen FIFO threshold triggered + * @arg MFXSTM32L152_IRQ_TS_FULL : Touch Screen FIFO Full + * @arg MFXSTM32L152_IRQ_TS_OVF : Touch Screen FIFO Overflow + * @retval None + */ +void mfxstm32l152_DisableITSource(uint16_t DeviceAddr, uint8_t Source) +{ + uint8_t tmp = 0; + + /* Get the current value of the INT_EN register */ + tmp = MFX_IO_Read(DeviceAddr, MFXSTM32L152_REG_ADR_IRQ_SRC_EN); + + /* Set the interrupts to be Enabled */ + tmp &= ~Source; + + /* Set the register */ + MFX_IO_Write(DeviceAddr, MFXSTM32L152_REG_ADR_IRQ_SRC_EN, tmp); +} + + +/** + * @brief Returns the selected Global interrupt source pending bit value + * @param DeviceAddr: Device address on communication Bus. + * @param Source: the Global interrupt source to be checked, could be: + * @arg MFXSTM32L152_IRQ_GPIO: IO interrupt + * @arg MFXSTM32L152_IRQ_IDD : IDD interrupt + * @arg MFXSTM32L152_IRQ_ERROR : Error interrupt + * @arg MFXSTM32L152_IRQ_TS_DET : Touch Screen Controller Touch Detected interrupt + * @arg MFXSTM32L152_IRQ_TS_NE : Touch Screen FIFO Not Empty + * @arg MFXSTM32L152_IRQ_TS_TH : Touch Screen FIFO threshold triggered + * @arg MFXSTM32L152_IRQ_TS_FULL : Touch Screen FIFO Full + * @arg MFXSTM32L152_IRQ_TS_OVF : Touch Screen FIFO Overflow + * @retval The value of the checked Global interrupt source status. + */ +uint8_t mfxstm32l152_GlobalITStatus(uint16_t DeviceAddr, uint8_t Source) +{ + /* Return the global IT source status (pending or not)*/ + return((MFX_IO_Read(DeviceAddr, MFXSTM32L152_REG_ADR_IRQ_PENDING) & Source)); +} + +/** + * @brief Clear the selected Global interrupt pending bit(s) + * @param DeviceAddr: Device address on communication Bus. + * @param Source: the Global interrupt source to be cleared, could be any combination + * of the below values. The acknowledge signal for MFXSTM32L152_GPIOs configured in input + * with interrupt is not on this register but in IRQ_GPI_ACK1, IRQ_GPI_ACK2 registers. + * @arg MFXSTM32L152_IRQ_IDD : IDD interrupt + * @arg MFXSTM32L152_IRQ_ERROR : Error interrupt + * @arg MFXSTM32L152_IRQ_TS_DET : Touch Screen Controller Touch Detected interrupt + * @arg MFXSTM32L152_IRQ_TS_NE : Touch Screen FIFO Not Empty + * @arg MFXSTM32L152_IRQ_TS_TH : Touch Screen FIFO threshold triggered + * @arg MFXSTM32L152_IRQ_TS_FULL : Touch Screen FIFO Full + * @arg MFXSTM32L152_IRQ_TS_OVF : Touch Screen FIFO Overflow + * /\/\ IMPORTANT NOTE /\/\ must not use MFXSTM32L152_IRQ_GPIO as argument, see IRQ_GPI_ACK1 and IRQ_GPI_ACK2 registers + * @retval None + */ +void mfxstm32l152_ClearGlobalIT(uint16_t DeviceAddr, uint8_t Source) +{ + /* Write 1 to the bits that have to be cleared */ + MFX_IO_Write(DeviceAddr, MFXSTM32L152_REG_ADR_IRQ_ACK, Source); +} + +/** + * @brief Set the global interrupt Polarity of IRQ_OUT_PIN. + * @param DeviceAddr: Device address on communication Bus. + * @param Polarity: the IT mode polarity, could be one of the following values: + * @arg MFXSTM32L152_OUT_PIN_POLARITY_LOW: Interrupt output line is active Low edge + * @arg MFXSTM32L152_OUT_PIN_POLARITY_HIGH: Interrupt line output is active High edge + * @retval None + */ +void mfxstm32l152_SetIrqOutPinPolarity(uint16_t DeviceAddr, uint8_t Polarity) +{ + uint8_t tmp = 0; + + /* Get the current register value */ + tmp = MFX_IO_Read(DeviceAddr, MFXSTM32L152_REG_ADR_MFX_IRQ_OUT); + + /* Mask the polarity bits */ + tmp &= ~(uint8_t)0x02; + + /* Modify the Interrupt Output line configuration */ + tmp |= Polarity; + + /* Set the new register value */ + MFX_IO_Write(DeviceAddr, MFXSTM32L152_REG_ADR_MFX_IRQ_OUT, tmp); + + /* Wait for 1 ms for MFX to change IRQ_out pin config, before activate it */ + MFX_IO_Delay(1); + +} + +/** + * @brief Set the global interrupt Type of IRQ_OUT_PIN. + * @param DeviceAddr: Device address on communication Bus. + * @param Type: Interrupt line activity type, could be one of the following values: + * @arg MFXSTM32L152_OUT_PIN_TYPE_OPENDRAIN: Open Drain output Interrupt line + * @arg MFXSTM32L152_OUT_PIN_TYPE_PUSHPULL: Push Pull output Interrupt line + * @retval None + */ +void mfxstm32l152_SetIrqOutPinType(uint16_t DeviceAddr, uint8_t Type) +{ + uint8_t tmp = 0; + + /* Get the current register value */ + tmp = MFX_IO_Read(DeviceAddr, MFXSTM32L152_REG_ADR_MFX_IRQ_OUT); + + /* Mask the type bits */ + tmp &= ~(uint8_t)0x01; + + /* Modify the Interrupt Output line configuration */ + tmp |= Type; + + /* Set the new register value */ + MFX_IO_Write(DeviceAddr, MFXSTM32L152_REG_ADR_MFX_IRQ_OUT, tmp); + + /* Wait for 1 ms for MFX to change IRQ_out pin config, before activate it */ + MFX_IO_Delay(1); + +} + + +/* ------------------------------------------------------------------ */ +/* ----------------------- GPIO ------------------------------------- */ +/* ------------------------------------------------------------------ */ + + +/** + * @brief Start the IO functionality used and enable the AF for selected IO pin(s). + * @param DeviceAddr: Device address on communication Bus. + * @param AF_en: 0 to disable, else enabled. + * @retval None + */ +void mfxstm32l152_IO_Start(uint16_t DeviceAddr, uint32_t IO_Pin) +{ + uint8_t mode; + + /* Get the current register value */ + mode = MFX_IO_Read(DeviceAddr, MFXSTM32L152_REG_ADR_SYS_CTRL); + + /* Set the IO Functionalities to be Enabled */ + mode |= MFXSTM32L152_GPIO_EN; + + /* Enable ALTERNATE functions */ + /* AGPIO[0..3] can be either IDD or GPIO */ + /* AGPIO[4..7] can be either TS or GPIO */ + /* if IDD or TS are enabled no matter the value this bit GPIO are not available for those pins */ + /* however the MFX will waste some cycles to to handle these potential GPIO (pooling, etc) */ + /* so if IDD and TS are both active it is better to let ALTERNATE off (0) */ + /* if however IDD or TS are not connected then set it on gives more GPIOs availability */ + /* remind that AGPIO are less efficient then normal GPIO (They use pooling rather then EXTI */ + if (IO_Pin > 0xFFFF) + { + mode |= MFXSTM32L152_ALTERNATE_GPIO_EN; + } + else + { + mode &= ~MFXSTM32L152_ALTERNATE_GPIO_EN; + } + + /* Write the new register value */ + MFX_IO_Write(DeviceAddr, MFXSTM32L152_REG_ADR_SYS_CTRL, mode); + + /* Wait for 1 ms for MFX to change IRQ_out pin config, before activate it */ + MFX_IO_Delay(1); +} + +/** + * @brief Configures the IO pin(s) according to IO mode structure value. + * @param DeviceAddr: Device address on communication Bus. + * @param IO_Pin: The output pin to be set or reset. This parameter can be one + * of the following values: + * @arg MFXSTM32L152_GPIO_PIN_x: where x can be from 0 to 23. + * @param IO_Mode: The IO pin mode to configure, could be one of the following values: + * @arg IO_MODE_INPUT + * @arg IO_MODE_OUTPUT + * @arg IO_MODE_IT_RISING_EDGE + * @arg IO_MODE_IT_FALLING_EDGE + * @arg IO_MODE_IT_LOW_LEVEL + * @arg IO_MODE_IT_HIGH_LEVEL + * @arg IO_MODE_INPUT_PU, + * @arg IO_MODE_INPUT_PD, + * @arg IO_MODE_OUTPUT_OD_PU, + * @arg IO_MODE_OUTPUT_OD_PD, + * @arg IO_MODE_OUTPUT_PP_PU, + * @arg IO_MODE_OUTPUT_PP_PD, + * @arg IO_MODE_IT_RISING_EDGE_PU + * @arg IO_MODE_IT_FALLING_EDGE_PU + * @arg IO_MODE_IT_LOW_LEVEL_PU + * @arg IO_MODE_IT_HIGH_LEVEL_PU + * @arg IO_MODE_IT_RISING_EDGE_PD + * @arg IO_MODE_IT_FALLING_EDGE_PD + * @arg IO_MODE_IT_LOW_LEVEL_PD + * @arg IO_MODE_IT_HIGH_LEVEL_PD + * @retval None + */ +uint8_t mfxstm32l152_IO_Config(uint16_t DeviceAddr, uint32_t IO_Pin, IO_ModeTypedef IO_Mode) +{ + uint8_t error_code = 0; + + /* Configure IO pin according to selected IO mode */ + switch(IO_Mode) + { + case IO_MODE_OFF: /* Off or analog mode */ + case IO_MODE_ANALOG: /* Off or analog mode */ + mfxstm32l152_IO_DisablePinIT(DeviceAddr, IO_Pin); /* first disable IT */ + mfxstm32l152_IO_InitPin(DeviceAddr, IO_Pin, MFXSTM32L152_GPIO_DIR_IN); + mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_TYPE1, IO_Pin, MFXSTM32L152_GPI_WITHOUT_PULL_RESISTOR); + mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_PUPD1, IO_Pin, MFXSTM32L152_GPIO_PULL_DOWN); + break; + + case IO_MODE_INPUT: /* Input mode */ + mfxstm32l152_IO_DisablePinIT(DeviceAddr, IO_Pin); /* first disable IT */ + mfxstm32l152_IO_InitPin(DeviceAddr, IO_Pin, MFXSTM32L152_GPIO_DIR_IN); + mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_TYPE1, IO_Pin, MFXSTM32L152_GPI_WITHOUT_PULL_RESISTOR); + mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_PUPD1, IO_Pin, MFXSTM32L152_GPIO_PULL_UP); + break; + + case IO_MODE_INPUT_PU: /* Input mode */ + mfxstm32l152_IO_DisablePinIT(DeviceAddr, IO_Pin); /* first disable IT */ + mfxstm32l152_IO_InitPin(DeviceAddr, IO_Pin, MFXSTM32L152_GPIO_DIR_IN); + mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_TYPE1, IO_Pin, MFXSTM32L152_GPI_WITH_PULL_RESISTOR); + mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_PUPD1, IO_Pin, MFXSTM32L152_GPIO_PULL_UP); + break; + + case IO_MODE_INPUT_PD: /* Input mode */ + mfxstm32l152_IO_DisablePinIT(DeviceAddr, IO_Pin); /* first disable IT */ + mfxstm32l152_IO_InitPin(DeviceAddr, IO_Pin, MFXSTM32L152_GPIO_DIR_IN); + mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_TYPE1, IO_Pin, MFXSTM32L152_GPI_WITH_PULL_RESISTOR); + mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_PUPD1, IO_Pin, MFXSTM32L152_GPIO_PULL_DOWN); + break; + + case IO_MODE_OUTPUT: /* Output mode */ + case IO_MODE_OUTPUT_PP_PD: /* Output mode */ + mfxstm32l152_IO_DisablePinIT(DeviceAddr, IO_Pin); /* first disable IT */ + mfxstm32l152_IO_InitPin(DeviceAddr, IO_Pin, MFXSTM32L152_GPIO_DIR_OUT); + mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_TYPE1, IO_Pin, MFXSTM32L152_GPO_PUSH_PULL); + mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_PUPD1, IO_Pin, MFXSTM32L152_GPIO_PULL_DOWN); + break; + + case IO_MODE_OUTPUT_PP_PU: /* Output mode */ + mfxstm32l152_IO_DisablePinIT(DeviceAddr, IO_Pin); /* first disable IT */ + mfxstm32l152_IO_InitPin(DeviceAddr, IO_Pin, MFXSTM32L152_GPIO_DIR_OUT); + mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_TYPE1, IO_Pin, MFXSTM32L152_GPO_PUSH_PULL); + mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_PUPD1, IO_Pin, MFXSTM32L152_GPIO_PULL_UP); + break; + + case IO_MODE_OUTPUT_OD_PD: /* Output mode */ + mfxstm32l152_IO_DisablePinIT(DeviceAddr, IO_Pin); /* first disable IT */ + mfxstm32l152_IO_InitPin(DeviceAddr, IO_Pin, MFXSTM32L152_GPIO_DIR_OUT); + mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_TYPE1, IO_Pin, MFXSTM32L152_GPO_OPEN_DRAIN); + mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_PUPD1, IO_Pin, MFXSTM32L152_GPIO_PULL_DOWN); + break; + + case IO_MODE_OUTPUT_OD_PU: /* Output mode */ + mfxstm32l152_IO_DisablePinIT(DeviceAddr, IO_Pin); /* first disable IT */ + mfxstm32l152_IO_InitPin(DeviceAddr, IO_Pin, MFXSTM32L152_GPIO_DIR_OUT); + mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_TYPE1, IO_Pin, MFXSTM32L152_GPO_OPEN_DRAIN); + mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_PUPD1, IO_Pin, MFXSTM32L152_GPIO_PULL_UP); + break; + + case IO_MODE_IT_RISING_EDGE: /* Interrupt rising edge mode */ + mfxstm32l152_IO_EnableIT(DeviceAddr); + mfxstm32l152_IO_InitPin(DeviceAddr, IO_Pin, MFXSTM32L152_GPIO_DIR_IN); + mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_TYPE1, IO_Pin, MFXSTM32L152_GPI_WITHOUT_PULL_RESISTOR); + mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_PUPD1, IO_Pin, MFXSTM32L152_GPIO_PULL_UP); + mfxstm32l152_IO_SetIrqEvtMode(DeviceAddr, IO_Pin, MFXSTM32L152_IRQ_GPI_EVT_EDGE); + mfxstm32l152_IO_SetIrqTypeMode(DeviceAddr, IO_Pin, MFXSTM32L152_IRQ_GPI_TYPE_HLRE); + mfxstm32l152_IO_EnablePinIT(DeviceAddr, IO_Pin); /* last to do: enable IT */ + break; + + case IO_MODE_IT_RISING_EDGE_PU: /* Interrupt rising edge mode */ + mfxstm32l152_IO_EnableIT(DeviceAddr); + mfxstm32l152_IO_InitPin(DeviceAddr, IO_Pin, MFXSTM32L152_GPIO_DIR_IN); + mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_TYPE1, IO_Pin, MFXSTM32L152_GPI_WITH_PULL_RESISTOR); + mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_PUPD1, IO_Pin, MFXSTM32L152_GPIO_PULL_UP); + mfxstm32l152_IO_SetIrqEvtMode(DeviceAddr, IO_Pin, MFXSTM32L152_IRQ_GPI_EVT_EDGE); + mfxstm32l152_IO_SetIrqTypeMode(DeviceAddr, IO_Pin, MFXSTM32L152_IRQ_GPI_TYPE_HLRE); + mfxstm32l152_IO_EnablePinIT(DeviceAddr, IO_Pin); /* last to do: enable IT */ + break; + + case IO_MODE_IT_RISING_EDGE_PD: /* Interrupt rising edge mode */ + mfxstm32l152_IO_EnableIT(DeviceAddr); + mfxstm32l152_IO_InitPin(DeviceAddr, IO_Pin, MFXSTM32L152_GPIO_DIR_IN); + mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_TYPE1, IO_Pin, MFXSTM32L152_GPI_WITH_PULL_RESISTOR); + mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_PUPD1, IO_Pin, MFXSTM32L152_GPIO_PULL_DOWN); + mfxstm32l152_IO_SetIrqEvtMode(DeviceAddr, IO_Pin, MFXSTM32L152_IRQ_GPI_EVT_EDGE); + mfxstm32l152_IO_SetIrqTypeMode(DeviceAddr, IO_Pin, MFXSTM32L152_IRQ_GPI_TYPE_HLRE); + mfxstm32l152_IO_EnablePinIT(DeviceAddr, IO_Pin); /* last to do: enable IT */ + break; + + case IO_MODE_IT_FALLING_EDGE: /* Interrupt falling edge mode */ + mfxstm32l152_IO_EnableIT(DeviceAddr); + mfxstm32l152_IO_InitPin(DeviceAddr, IO_Pin, MFXSTM32L152_GPIO_DIR_IN); + mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_TYPE1, IO_Pin, MFXSTM32L152_GPI_WITHOUT_PULL_RESISTOR); + mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_PUPD1, IO_Pin, MFXSTM32L152_GPIO_PULL_UP); + mfxstm32l152_IO_SetIrqEvtMode(DeviceAddr, IO_Pin, MFXSTM32L152_IRQ_GPI_EVT_EDGE); + mfxstm32l152_IO_SetIrqTypeMode(DeviceAddr, IO_Pin, MFXSTM32L152_IRQ_GPI_TYPE_LLFE); + mfxstm32l152_IO_EnablePinIT(DeviceAddr, IO_Pin); /* last to do: enable IT */ + break; + + case IO_MODE_IT_FALLING_EDGE_PU: /* Interrupt falling edge mode */ + mfxstm32l152_IO_EnableIT(DeviceAddr); + mfxstm32l152_IO_InitPin(DeviceAddr, IO_Pin, MFXSTM32L152_GPIO_DIR_IN); + mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_TYPE1, IO_Pin, MFXSTM32L152_GPI_WITH_PULL_RESISTOR); + mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_PUPD1, IO_Pin, MFXSTM32L152_GPIO_PULL_UP); + mfxstm32l152_IO_SetIrqEvtMode(DeviceAddr, IO_Pin, MFXSTM32L152_IRQ_GPI_EVT_EDGE); + mfxstm32l152_IO_SetIrqTypeMode(DeviceAddr, IO_Pin, MFXSTM32L152_IRQ_GPI_TYPE_LLFE); + mfxstm32l152_IO_EnablePinIT(DeviceAddr, IO_Pin); /* last to do: enable IT */ + break; + + case IO_MODE_IT_FALLING_EDGE_PD: /* Interrupt falling edge mode */ + mfxstm32l152_IO_EnableIT(DeviceAddr); + mfxstm32l152_IO_InitPin(DeviceAddr, IO_Pin, MFXSTM32L152_GPIO_DIR_IN); + mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_TYPE1, IO_Pin, MFXSTM32L152_GPI_WITH_PULL_RESISTOR); + mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_PUPD1, IO_Pin, MFXSTM32L152_GPIO_PULL_DOWN); + mfxstm32l152_IO_SetIrqEvtMode(DeviceAddr, IO_Pin, MFXSTM32L152_IRQ_GPI_EVT_EDGE); + mfxstm32l152_IO_SetIrqTypeMode(DeviceAddr, IO_Pin, MFXSTM32L152_IRQ_GPI_TYPE_LLFE); + mfxstm32l152_IO_EnablePinIT(DeviceAddr, IO_Pin); /* last to do: enable IT */ + break; + + case IO_MODE_IT_LOW_LEVEL: /* Low level interrupt mode */ + mfxstm32l152_IO_EnableIT(DeviceAddr); + mfxstm32l152_IO_InitPin(DeviceAddr, IO_Pin, MFXSTM32L152_GPIO_DIR_IN); + mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_TYPE1, IO_Pin, MFXSTM32L152_GPI_WITHOUT_PULL_RESISTOR); + mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_PUPD1, IO_Pin, MFXSTM32L152_GPIO_PULL_UP); + mfxstm32l152_IO_SetIrqEvtMode(DeviceAddr, IO_Pin, MFXSTM32L152_IRQ_GPI_EVT_LEVEL); + mfxstm32l152_IO_SetIrqTypeMode(DeviceAddr, IO_Pin, MFXSTM32L152_IRQ_GPI_TYPE_LLFE); + mfxstm32l152_IO_EnablePinIT(DeviceAddr, IO_Pin); /* last to do: enable IT */ + break; + + case IO_MODE_IT_LOW_LEVEL_PU: /* Low level interrupt mode */ + mfxstm32l152_IO_EnableIT(DeviceAddr); + mfxstm32l152_IO_InitPin(DeviceAddr, IO_Pin, MFXSTM32L152_GPIO_DIR_IN); + mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_TYPE1, IO_Pin, MFXSTM32L152_GPI_WITH_PULL_RESISTOR); + mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_PUPD1, IO_Pin, MFXSTM32L152_GPIO_PULL_UP); + mfxstm32l152_IO_SetIrqEvtMode(DeviceAddr, IO_Pin, MFXSTM32L152_IRQ_GPI_EVT_LEVEL); + mfxstm32l152_IO_SetIrqTypeMode(DeviceAddr, IO_Pin, MFXSTM32L152_IRQ_GPI_TYPE_LLFE); + mfxstm32l152_IO_EnablePinIT(DeviceAddr, IO_Pin); /* last to do: enable IT */ + break; + + case IO_MODE_IT_LOW_LEVEL_PD: /* Low level interrupt mode */ + mfxstm32l152_IO_EnableIT(DeviceAddr); + mfxstm32l152_IO_InitPin(DeviceAddr, IO_Pin, MFXSTM32L152_GPIO_DIR_IN); + mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_TYPE1, IO_Pin, MFXSTM32L152_GPI_WITH_PULL_RESISTOR); + mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_PUPD1, IO_Pin, MFXSTM32L152_GPIO_PULL_DOWN); + mfxstm32l152_IO_SetIrqEvtMode(DeviceAddr, IO_Pin, MFXSTM32L152_IRQ_GPI_EVT_LEVEL); + mfxstm32l152_IO_SetIrqTypeMode(DeviceAddr, IO_Pin, MFXSTM32L152_IRQ_GPI_TYPE_LLFE); + mfxstm32l152_IO_EnablePinIT(DeviceAddr, IO_Pin); /* last to do: enable IT */ + break; + + case IO_MODE_IT_HIGH_LEVEL: /* High level interrupt mode */ + mfxstm32l152_IO_EnableIT(DeviceAddr); + mfxstm32l152_IO_InitPin(DeviceAddr, IO_Pin, MFXSTM32L152_GPIO_DIR_IN); + mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_TYPE1, IO_Pin, MFXSTM32L152_GPI_WITHOUT_PULL_RESISTOR); + mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_PUPD1, IO_Pin, MFXSTM32L152_GPIO_PULL_UP); + mfxstm32l152_IO_SetIrqEvtMode(DeviceAddr, IO_Pin, MFXSTM32L152_IRQ_GPI_EVT_LEVEL); + mfxstm32l152_IO_SetIrqTypeMode(DeviceAddr, IO_Pin, MFXSTM32L152_IRQ_GPI_TYPE_HLRE); + mfxstm32l152_IO_EnablePinIT(DeviceAddr, IO_Pin); /* last to do: enable IT */ + break; + + case IO_MODE_IT_HIGH_LEVEL_PU: /* High level interrupt mode */ + mfxstm32l152_IO_EnableIT(DeviceAddr); + mfxstm32l152_IO_InitPin(DeviceAddr, IO_Pin, MFXSTM32L152_GPIO_DIR_IN); + mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_TYPE1, IO_Pin, MFXSTM32L152_GPI_WITH_PULL_RESISTOR); + mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_PUPD1, IO_Pin, MFXSTM32L152_GPIO_PULL_UP); + mfxstm32l152_IO_SetIrqEvtMode(DeviceAddr, IO_Pin, MFXSTM32L152_IRQ_GPI_EVT_LEVEL); + mfxstm32l152_IO_SetIrqTypeMode(DeviceAddr, IO_Pin, MFXSTM32L152_IRQ_GPI_TYPE_HLRE); + mfxstm32l152_IO_EnablePinIT(DeviceAddr, IO_Pin); /* last to do: enable IT */ + break; + + case IO_MODE_IT_HIGH_LEVEL_PD: /* High level interrupt mode */ + mfxstm32l152_IO_EnableIT(DeviceAddr); + mfxstm32l152_IO_InitPin(DeviceAddr, IO_Pin, MFXSTM32L152_GPIO_DIR_IN); + mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_TYPE1, IO_Pin, MFXSTM32L152_GPI_WITH_PULL_RESISTOR); + mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_PUPD1, IO_Pin, MFXSTM32L152_GPIO_PULL_DOWN); + mfxstm32l152_IO_SetIrqEvtMode(DeviceAddr, IO_Pin, MFXSTM32L152_IRQ_GPI_EVT_LEVEL); + mfxstm32l152_IO_SetIrqTypeMode(DeviceAddr, IO_Pin, MFXSTM32L152_IRQ_GPI_TYPE_HLRE); + mfxstm32l152_IO_EnablePinIT(DeviceAddr, IO_Pin); /* last to do: enable IT */ + break; + + default: + error_code = (uint8_t) IO_Mode; + break; + } + + return error_code; +} + +/** + * @brief Initialize the selected IO pin direction. + * @param DeviceAddr: Device address on communication Bus. + * @param IO_Pin: The IO pin to be configured. This parameter could be any + * combination of the following values: + * @arg MFXSTM32L152_GPIO_PIN_x: Where x can be from 0 to 23. + * @param Direction: could be MFXSTM32L152_GPIO_DIR_IN or MFXSTM32L152_GPIO_DIR_OUT. + * @retval None + */ +void mfxstm32l152_IO_InitPin(uint16_t DeviceAddr, uint32_t IO_Pin, uint8_t Direction) +{ + mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_DIR1, IO_Pin, Direction); +} + +/** + * @brief Set the global interrupt Type. + * @param DeviceAddr: Device address on communication Bus. + * @param IO_Pin: The IO pin to be configured. This parameter could be any + * combination of the following values: + * @arg MFXSTM32L152_GPIO_PIN_x: Where x can be from 0 to 23. + * @param Evt: Interrupt line activity type, could be one of the following values: + * @arg MFXSTM32L152_IRQ_GPI_EVT_LEVEL: Interrupt line is active in level model + * @arg MFXSTM32L152_IRQ_GPI_EVT_EDGE: Interrupt line is active in edge model + * @retval None + */ +void mfxstm32l152_IO_SetIrqEvtMode(uint16_t DeviceAddr, uint32_t IO_Pin, uint8_t Evt) +{ + mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_IRQ_GPI_EVT1, IO_Pin, Evt); + MFX_IO_Delay(1); +} + +/** + * @brief Configure the Edge for which a transition is detectable for the + * selected pin. + * @param DeviceAddr: Device address on communication Bus. + * @param IO_Pin: The IO pin to be configured. This parameter could be any + * combination of the following values: + * @arg MFXSTM32L152_GPIO_PIN_x: Where x can be from 0 to 23. + * @param Evt: Interrupt line activity type, could be one of the following values: + * @arg MFXSTM32L152_IRQ_GPI_TYPE_LLFE: Interrupt line is active in Low Level or Falling Edge + * @arg MFXSTM32L152_IRQ_GPI_TYPE_HLRE: Interrupt line is active in High Level or Rising Edge + * @retval None + */ +void mfxstm32l152_IO_SetIrqTypeMode(uint16_t DeviceAddr, uint32_t IO_Pin, uint8_t Type) +{ + mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_IRQ_GPI_TYPE1, IO_Pin, Type); + MFX_IO_Delay(1); +} + +/** + * @brief When GPIO is in output mode, puts the corresponding GPO in High (1) or Low (0) level. + * @param DeviceAddr: Device address on communication Bus. + * @param IO_Pin: The output pin to be set or reset. This parameter can be one + * of the following values: + * @arg MFXSTM32L152_GPIO_PIN_x: where x can be from 0 to 23. + * @param PinState: The new IO pin state. + * @retval None + */ +void mfxstm32l152_IO_WritePin(uint16_t DeviceAddr, uint32_t IO_Pin, uint8_t PinState) +{ + /* Apply the bit value to the selected pin */ + if (PinState != 0) + { + /* Set the SET register */ + mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPO_SET1, IO_Pin, 1); + } + else + { + /* Set the CLEAR register */ + mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPO_CLR1, IO_Pin, 1); + } +} + +/** + * @brief Return the state of the selected IO pin(s). + * @param DeviceAddr: Device address on communication Bus. + * @param IO_Pin: The output pin to be set or reset. This parameter can be one + * of the following values: + * @arg MFXSTM32L152_GPIO_PIN_x: where x can be from 0 to 23. + * @retval IO pin(s) state. + */ +uint32_t mfxstm32l152_IO_ReadPin(uint16_t DeviceAddr, uint32_t IO_Pin) +{ + uint32_t tmp1 = 0; + uint32_t tmp2 = 0; + uint32_t tmp3 = 0; + + if(IO_Pin & 0x000000FF) + { + tmp1 = (uint32_t) MFX_IO_Read(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_STATE1); + } + if(IO_Pin & 0x0000FF00) + { + tmp2 = (uint32_t) MFX_IO_Read(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_STATE2); + } + if(IO_Pin & 0x00FF0000) + { + tmp3 = (uint32_t) MFX_IO_Read(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_STATE3); + } + + tmp3 = tmp1 + (tmp2 << 8) + (tmp3 << 16); + + return(tmp3 & IO_Pin); +} + +/** + * @brief Enable the global IO interrupt source. + * @param DeviceAddr: Device address on communication Bus. + * @retval None + */ +void mfxstm32l152_IO_EnableIT(uint16_t DeviceAddr) +{ + MFX_IO_ITConfig(); + + /* Enable global IO IT source */ + mfxstm32l152_EnableITSource(DeviceAddr, MFXSTM32L152_IRQ_GPIO); +} + +/** + * @brief Disable the global IO interrupt source. + * @param DeviceAddr: Device address on communication Bus. + * @retval None + */ +void mfxstm32l152_IO_DisableIT(uint16_t DeviceAddr) +{ + /* Disable global IO IT source */ + mfxstm32l152_DisableITSource(DeviceAddr, MFXSTM32L152_IRQ_GPIO); +} + +/** + * @brief Enable interrupt mode for the selected IO pin(s). + * @param DeviceAddr: Device address on communication Bus. + * @param IO_Pin: The IO interrupt to be enabled. This parameter could be any + * combination of the following values: + * @arg MFXSTM32L152_GPIO_PIN_x: where x can be from 0 to 23. + * @retval None + */ +void mfxstm32l152_IO_EnablePinIT(uint16_t DeviceAddr, uint32_t IO_Pin) +{ + mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_IRQ_GPI_SRC1, IO_Pin, 1); +} + +/** + * @brief Disable interrupt mode for the selected IO pin(s). + * @param DeviceAddr: Device address on communication Bus. + * @param IO_Pin: The IO interrupt to be disabled. This parameter could be any + * combination of the following values: + * @arg MFXSTM32L152_GPIO_PIN_x: where x can be from 0 to 23. + * @retval None + */ +void mfxstm32l152_IO_DisablePinIT(uint16_t DeviceAddr, uint32_t IO_Pin) +{ + mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_IRQ_GPI_SRC1, IO_Pin, 0); +} + + +/** + * @brief Check the status of the selected IO interrupt pending bit + * @param DeviceAddr: Device address on communication Bus. + * @param IO_Pin: The IO interrupt to be checked could be: + * @arg MFXSTM32L152_GPIO_PIN_x Where x can be from 0 to 23. + * @retval Status of the checked IO pin(s). + */ +uint32_t mfxstm32l152_IO_ITStatus(uint16_t DeviceAddr, uint32_t IO_Pin) +{ + /* Get the Interrupt status */ + uint8_t tmp1 = 0; + uint16_t tmp2 = 0; + uint32_t tmp3 = 0; + + if(IO_Pin & 0xFF) + { + tmp1 = MFX_IO_Read(DeviceAddr, MFXSTM32L152_REG_ADR_IRQ_GPI_PENDING1); + } + if(IO_Pin & 0xFFFF00) + { + tmp2 = (uint16_t) MFX_IO_Read(DeviceAddr, MFXSTM32L152_REG_ADR_IRQ_GPI_PENDING2); + } + if(IO_Pin & 0xFFFF0000) + { + tmp3 = (uint32_t) MFX_IO_Read(DeviceAddr, MFXSTM32L152_REG_ADR_IRQ_GPI_PENDING3); + } + + tmp3 = tmp1 + (tmp2 << 8) + (tmp3 << 16); + + return(tmp3 & IO_Pin); +} + +/** + * @brief Clear the selected IO interrupt pending bit(s). It clear automatically also the general MFXSTM32L152_REG_ADR_IRQ_PENDING + * @param DeviceAddr: Device address on communication Bus. + * @param IO_Pin: the IO interrupt to be cleared, could be: + * @arg MFXSTM32L152_GPIO_PIN_x: Where x can be from 0 to 23. + * @retval None + */ +void mfxstm32l152_IO_ClearIT(uint16_t DeviceAddr, uint32_t IO_Pin) +{ + /* Clear the IO IT pending bit(s) by acknowledging */ + /* it cleans automatically also the Global IRQ_GPIO */ + /* normally this function is called under interrupt */ + uint8_t pin_0_7, pin_8_15, pin_16_23; + + pin_0_7 = IO_Pin & 0x0000ff; + pin_8_15 = IO_Pin >> 8; + pin_8_15 = pin_8_15 & 0x00ff; + pin_16_23 = IO_Pin >> 16; + + if (pin_0_7) + { + MFX_IO_Write(DeviceAddr, MFXSTM32L152_REG_ADR_IRQ_GPI_ACK1, pin_0_7); + } + if (pin_8_15) + { + MFX_IO_Write(DeviceAddr, MFXSTM32L152_REG_ADR_IRQ_GPI_ACK2, pin_8_15); + } + if (pin_16_23) + { + MFX_IO_Write(DeviceAddr, MFXSTM32L152_REG_ADR_IRQ_GPI_ACK3, pin_16_23); + } +} + + +/** + * @brief Enable the AF for aGPIO. + * @param DeviceAddr: Device address on communication Bus. + * @retval None + */ +void mfxstm32l152_IO_EnableAF(uint16_t DeviceAddr) +{ + uint8_t mode; + + /* Get the current register value */ + mode = MFX_IO_Read(DeviceAddr, MFXSTM32L152_REG_ADR_SYS_CTRL); + + /* Enable ALTERNATE functions */ + /* AGPIO[0..3] can be either IDD or GPIO */ + /* AGPIO[4..7] can be either TS or GPIO */ + /* if IDD or TS are enabled no matter the value this bit GPIO are not available for those pins */ + /* however the MFX will waste some cycles to to handle these potential GPIO (pooling, etc) */ + /* so if IDD and TS are both active it is better to let ALTERNATE disabled (0) */ + /* if however IDD or TS are not connected then set it on gives more GPIOs availability */ + /* remind that AGPIO are less efficient then normal GPIO (they use pooling rather then EXTI) */ + mode |= MFXSTM32L152_ALTERNATE_GPIO_EN; + + /* Write the new register value */ + MFX_IO_Write(DeviceAddr, MFXSTM32L152_REG_ADR_SYS_CTRL, mode); +} + +/** + * @brief Disable the AF for aGPIO. + * @param DeviceAddr: Device address on communication Bus. + * @retval None + */ + void mfxstm32l152_IO_DisableAF(uint16_t DeviceAddr) +{ + uint8_t mode; + + /* Get the current register value */ + mode = MFX_IO_Read(DeviceAddr, MFXSTM32L152_REG_ADR_SYS_CTRL); + + /* Enable ALTERNATE functions */ + /* AGPIO[0..3] can be either IDD or GPIO */ + /* AGPIO[4..7] can be either TS or GPIO */ + /* if IDD or TS are enabled no matter the value this bit GPIO are not available for those pins */ + /* however the MFX will waste some cycles to to handle these potential GPIO (pooling, etc) */ + /* so if IDD and TS are both active it is better to let ALTERNATE disabled (0) */ + /* if however IDD or TS are not connected then set it on gives more GPIOs availability */ + /* remind that AGPIO are less efficient then normal GPIO (they use pooling rather then EXTI) */ + mode &= ~MFXSTM32L152_ALTERNATE_GPIO_EN; + + /* Write the new register value */ + MFX_IO_Write(DeviceAddr, MFXSTM32L152_REG_ADR_SYS_CTRL, mode); + +} + + +/* ------------------------------------------------------------------ */ +/* --------------------- TOUCH SCREEN ------------------------------- */ +/* ------------------------------------------------------------------ */ + +/** + * @brief Configures the touch Screen Controller (Single point detection) + * @param DeviceAddr: Device address on communication Bus. + * @retval None. + */ +void mfxstm32l152_TS_Start(uint16_t DeviceAddr) +{ + uint8_t mode; + + /* Get the current register value */ + mode = MFX_IO_Read(DeviceAddr, MFXSTM32L152_REG_ADR_SYS_CTRL); + + /* Set the Functionalities to be Enabled */ + mode |= MFXSTM32L152_TS_EN; + + /* Set the new register value */ + MFX_IO_Write(DeviceAddr, MFXSTM32L152_REG_ADR_SYS_CTRL, mode); + + /* Wait for 2 ms */ + MFX_IO_Delay(2); + + /* Select 2 nF filter capacitor */ + /* Configuration: + - Touch average control : 4 samples + - Touch delay time : 500 uS + - Panel driver setting time: 500 uS + */ + MFX_IO_Write(DeviceAddr, MFXSTM32L152_TS_SETTLING, 0x32); + MFX_IO_Write(DeviceAddr, MFXSTM32L152_TS_TOUCH_DET_DELAY, 0x5); + MFX_IO_Write(DeviceAddr, MFXSTM32L152_TS_AVE, 0x04); + + /* Configure the Touch FIFO threshold: single point reading */ + MFX_IO_Write(DeviceAddr, MFXSTM32L152_TS_FIFO_TH, 0x01); + + /* Clear the FIFO memory content. */ + MFX_IO_Write(DeviceAddr, MFXSTM32L152_TS_FIFO_TH, MFXSTM32L152_TS_CLEAR_FIFO); + + /* Touch screen control configuration : + - No window tracking index + */ + MFX_IO_Write(DeviceAddr, MFXSTM32L152_TS_TRACK, 0x00); + + + /* Clear all the IT status pending bits if any */ + mfxstm32l152_IO_ClearIT(DeviceAddr, 0xFFFFFF); + + /* Wait for 1 ms delay */ + MFX_IO_Delay(1); +} + +/** + * @brief Return if there is touch detected or not. + * @param DeviceAddr: Device address on communication Bus. + * @retval Touch detected state. + */ +uint8_t mfxstm32l152_TS_DetectTouch(uint16_t DeviceAddr) +{ + uint8_t state; + uint8_t ret = 0; + + state = MFX_IO_Read(DeviceAddr, MFXSTM32L152_TS_FIFO_STA); + state = ((state & (uint8_t)MFXSTM32L152_TS_CTRL_STATUS) == (uint8_t)MFXSTM32L152_TS_CTRL_STATUS); + + if(state > 0) + { + if(MFX_IO_Read(DeviceAddr, MFXSTM32L152_TS_FIFO_LEVEL) > 0) + { + ret = 1; + } + } + + return ret; +} + +/** + * @brief Get the touch screen X and Y positions values + * @param DeviceAddr: Device address on communication Bus. + * @param X: Pointer to X position value + * @param Y: Pointer to Y position value + * @retval None. + */ +void mfxstm32l152_TS_GetXY(uint16_t DeviceAddr, uint16_t *X, uint16_t *Y) +{ + uint8_t data_xy[3]; + + MFX_IO_ReadMultiple(DeviceAddr, MFXSTM32L152_TS_XY_DATA, data_xy, sizeof(data_xy)) ; + + /* Calculate positions values */ + *X = (data_xy[1]<<4) + (data_xy[0]>>4); + *Y = (data_xy[2]<<4) + (data_xy[0]&4); + + /* Reset the FIFO memory content. */ + MFX_IO_Write(DeviceAddr, MFXSTM32L152_TS_FIFO_TH, MFXSTM32L152_TS_CLEAR_FIFO); +} + +/** + * @brief Configure the selected source to generate a global interrupt or not + * @param DeviceAddr: Device address on communication Bus. + * @retval None + */ +void mfxstm32l152_TS_EnableIT(uint16_t DeviceAddr) +{ + MFX_IO_ITConfig(); + + /* Enable global TS IT source */ + mfxstm32l152_EnableITSource(DeviceAddr, MFXSTM32L152_IRQ_TS_DET); +} + +/** + * @brief Configure the selected source to generate a global interrupt or not + * @param DeviceAddr: Device address on communication Bus. + * @retval None + */ +void mfxstm32l152_TS_DisableIT(uint16_t DeviceAddr) +{ + /* Disable global TS IT source */ + mfxstm32l152_DisableITSource(DeviceAddr, MFXSTM32L152_IRQ_TS_DET); +} + +/** + * @brief Configure the selected source to generate a global interrupt or not + * @param DeviceAddr: Device address on communication Bus. + * @retval TS interrupts status + */ +uint8_t mfxstm32l152_TS_ITStatus(uint16_t DeviceAddr) +{ + /* Return TS interrupts status */ + return(mfxstm32l152_GlobalITStatus(DeviceAddr, MFXSTM32L152_IRQ_TS)); +} + +/** + * @brief Configure the selected source to generate a global interrupt or not + * @param DeviceAddr: Device address on communication Bus. + * @retval None + */ +void mfxstm32l152_TS_ClearIT(uint16_t DeviceAddr) +{ + /* Clear the global TS IT source */ + mfxstm32l152_ClearGlobalIT(DeviceAddr, MFXSTM32L152_IRQ_TS); +} + +/* ------------------------------------------------------------------ */ +/* --------------------- IDD MEASUREMENT ---------------------------- */ +/* ------------------------------------------------------------------ */ + +/** + * @brief Launch IDD current measurement + * @param DeviceAddr: Device address on communication Bus + * @retval None. + */ +void mfxstm32l152_IDD_Start(uint16_t DeviceAddr) +{ + uint8_t mode = 0; + + /* Get the current register value */ + mode = MFX_IO_Read((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_CTRL); + + /* Set the Functionalities to be enabled */ + mode |= MFXSTM32L152_IDD_CTRL_REQ; + + /* Start measurement campaign */ + MFX_IO_Write((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_CTRL, mode); +} + +/** + * @brief Configures the IDD current measurement + * @param DeviceAddr: Device address on communication Bus. + * @param MfxIddConfig: Parameters depending on hardware config. + * @retval None + */ +void mfxstm32l152_IDD_Config(uint16_t DeviceAddr, IDD_ConfigTypeDef MfxIddConfig) +{ + uint8_t value = 0; + uint8_t mode = 0; + + /* Get the current register value */ + mode = MFX_IO_Read((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_SYS_CTRL); + + if((mode & MFXSTM32L152_IDD_EN) != MFXSTM32L152_IDD_EN) + { + /* Set the Functionalities to be enabled */ + mode |= MFXSTM32L152_IDD_EN; + + /* Set the new register value */ + MFX_IO_Write((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_SYS_CTRL, mode); + } + + /* Control register setting: number of shunts */ + value = ((MfxIddConfig.ShuntNbUsed << 1) & MFXSTM32L152_IDD_CTRL_SHUNT_NB); + value |= (MfxIddConfig.VrefMeasurement & MFXSTM32L152_IDD_CTRL_VREF_DIS); + value |= (MfxIddConfig.Calibration & MFXSTM32L152_IDD_CTRL_CAL_DIS); + MFX_IO_Write((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_CTRL, value); + + /* Idd pre delay configuration: unit and value*/ + value = (MfxIddConfig.PreDelayUnit & MFXSTM32L152_IDD_PREDELAY_UNIT) | + (MfxIddConfig.PreDelayValue & MFXSTM32L152_IDD_PREDELAY_VALUE); + MFX_IO_Write((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_PRE_DELAY, value); + + /* Shunt 0 register value: MSB then LSB */ + value = (uint8_t) (MfxIddConfig.Shunt0Value >> 8); + MFX_IO_Write((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_SHUNT0_MSB, value); + value = (uint8_t) (MfxIddConfig.Shunt0Value); + MFX_IO_Write((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_SHUNT0_LSB, value); + + /* Shunt 1 register value: MSB then LSB */ + value = (uint8_t) (MfxIddConfig.Shunt1Value >> 8); + MFX_IO_Write((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_SHUNT1_MSB, value); + value = (uint8_t) (MfxIddConfig.Shunt1Value); + MFX_IO_Write((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_SHUNT1_LSB, value); + + /* Shunt 2 register value: MSB then LSB */ + value = (uint8_t) (MfxIddConfig.Shunt2Value >> 8); + MFX_IO_Write((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_SHUNT2_MSB, value); + value = (uint8_t) (MfxIddConfig.Shunt2Value); + MFX_IO_Write((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_SHUNT2_LSB, value); + + /* Shunt 3 register value: MSB then LSB */ + value = (uint8_t) (MfxIddConfig.Shunt3Value >> 8); + MFX_IO_Write((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_SHUNT3_MSB, value); + value = (uint8_t) (MfxIddConfig.Shunt3Value); + MFX_IO_Write((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_SHUNT3_LSB, value); + + /* Shunt 4 register value: MSB then LSB */ + value = (uint8_t) (MfxIddConfig.Shunt4Value >> 8); + MFX_IO_Write((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_SHUNT4_MSB, value); + value = (uint8_t) (MfxIddConfig.Shunt4Value); + MFX_IO_Write((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_SHUNT4_LSB, value); + + /* Shunt 0 stabilization delay */ + value = MfxIddConfig.Shunt0StabDelay; + MFX_IO_Write((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_SH0_STABILIZATION, value); + + /* Shunt 1 stabilization delay */ + value = MfxIddConfig.Shunt1StabDelay; + MFX_IO_Write((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_SH1_STABILIZATION, value); + + /* Shunt 2 stabilization delay */ + value = MfxIddConfig.Shunt2StabDelay; + MFX_IO_Write((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_SH2_STABILIZATION, value); + + /* Shunt 3 stabilization delay */ + value = MfxIddConfig.Shunt3StabDelay; + MFX_IO_Write((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_SH3_STABILIZATION, value); + + /* Shunt 4 stabilization delay */ + value = MfxIddConfig.Shunt4StabDelay; + MFX_IO_Write((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_SH4_STABILIZATION, value); + + /* Idd ampli gain value: MSB then LSB */ + value = (uint8_t) (MfxIddConfig.AmpliGain >> 8); + MFX_IO_Write((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_GAIN_MSB, value); + value = (uint8_t) (MfxIddConfig.AmpliGain); + MFX_IO_Write((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_GAIN_LSB, value); + + /* Idd VDD min value: MSB then LSB */ + value = (uint8_t) (MfxIddConfig.VddMin >> 8); + MFX_IO_Write((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_VDD_MIN_MSB, value); + value = (uint8_t) (MfxIddConfig.VddMin); + MFX_IO_Write((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_VDD_MIN_LSB, value); + + /* Idd number of measurements */ + value = MfxIddConfig.MeasureNb; + MFX_IO_Write((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_NBR_OF_MEAS, value); + + /* Idd delta delay configuration: unit and value */ + value = (MfxIddConfig.DeltaDelayUnit & MFXSTM32L152_IDD_DELTADELAY_UNIT) | + (MfxIddConfig.DeltaDelayValue & MFXSTM32L152_IDD_DELTADELAY_VALUE); + MFX_IO_Write((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_MEAS_DELTA_DELAY, value); + + /* Idd number of shut on board */ + value = MfxIddConfig.ShuntNbOnBoard; + MFX_IO_Write((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_SHUNTS_ON_BOARD, value); +} + +/** + * @brief This function allows to modify number of shunt used for a measurement + * @param DeviceAddr: Device address on communication Bus + * @retval None. + */ +void mfxstm32l152_IDD_ConfigShuntNbLimit(uint16_t DeviceAddr, uint8_t ShuntNbLimit) +{ + uint8_t mode = 0; + + /* Get the current register value */ + mode = MFX_IO_Read((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_CTRL); + + /* Clear number of shunt limit */ + mode &= ~(MFXSTM32L152_IDD_CTRL_SHUNT_NB); + + /* Clear number of shunt limit */ + mode |= ((ShuntNbLimit << 1) & MFXSTM32L152_IDD_CTRL_SHUNT_NB); + + /* Write noewx desired limit */ + MFX_IO_Write((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_CTRL, mode); +} + +/** + * @brief Get Idd current value + * @param DeviceAddr: Device address on communication Bus + * @param ReadValue: Pointer on value to be read + * @retval Idd value in 10 nA. + */ +void mfxstm32l152_IDD_GetValue(uint16_t DeviceAddr, uint32_t *ReadValue) +{ + uint8_t data[3]; + + MFX_IO_ReadMultiple((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_VALUE_MSB, data, sizeof(data)) ; + + /* Recompose Idd current value */ + *ReadValue = (data[0] << 16) | (data[1] << 8) | data[2]; + +} + +/** + * @brief Get Last shunt used for measurement + * @param DeviceAddr: Device address on communication Bus + * @retval Last shunt used + */ +uint8_t mfxstm32l152_IDD_GetShuntUsed(uint16_t DeviceAddr) +{ + return(MFX_IO_Read((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_SHUNT_USED)); +} + +/** + * @brief Configure mfx to enable Idd interrupt + * @param DeviceAddr: Device address on communication Bus. + * @retval None + */ +void mfxstm32l152_IDD_EnableIT(uint16_t DeviceAddr) +{ + MFX_IO_ITConfig(); + + /* Enable global IDD interrupt source */ + mfxstm32l152_EnableITSource(DeviceAddr, MFXSTM32L152_IRQ_IDD); +} + +/** + * @brief Clear Idd global interrupt + * @param DeviceAddr: Device address on communication Bus. + * @retval None + */ +void mfxstm32l152_IDD_ClearIT(uint16_t DeviceAddr) +{ + /* Clear the global IDD interrupt source */ + mfxstm32l152_ClearGlobalIT(DeviceAddr, MFXSTM32L152_IRQ_IDD); +} + +/** + * @brief get Idd interrupt status + * @param DeviceAddr: Device address on communication Bus. + * @retval IDD interrupts status + */ +uint8_t mfxstm32l152_IDD_GetITStatus(uint16_t DeviceAddr) +{ + /* Return IDD interrupt status */ + return(mfxstm32l152_GlobalITStatus(DeviceAddr, MFXSTM32L152_IRQ_IDD)); +} + +/** + * @brief disable Idd interrupt + * @param DeviceAddr: Device address on communication Bus. + * @retval None. + */ +void mfxstm32l152_IDD_DisableIT(uint16_t DeviceAddr) +{ + /* Disable global IDD interrupt source */ + mfxstm32l152_DisableITSource(DeviceAddr, MFXSTM32L152_IRQ_IDD); +} + + +/* ------------------------------------------------------------------ */ +/* --------------------- ERROR MANAGEMENT --------------------------- */ +/* ------------------------------------------------------------------ */ + +/** + * @brief Read Error Source. + * @param DeviceAddr: Device address on communication Bus. + * @retval Error message code with error source + */ +uint8_t mfxstm32l152_Error_ReadSrc(uint16_t DeviceAddr) +{ + /* Get the current source register value */ + return(MFX_IO_Read((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_ERROR_SRC)); +} + +/** + * @brief Read Error Message + * @param DeviceAddr: Device address on communication Bus. + * @retval Error message code with error source + */ +uint8_t mfxstm32l152_Error_ReadMsg(uint16_t DeviceAddr) +{ + /* Get the current message register value */ + return(MFX_IO_Read((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_ERROR_MSG)); +} + +/** + * @brief Enable Error global interrupt + * @param DeviceAddr: Device address on communication Bus. + * @retval None + */ + +void mfxstm32l152_Error_EnableIT(uint16_t DeviceAddr) +{ + MFX_IO_ITConfig(); + + /* Enable global Error interrupt source */ + mfxstm32l152_EnableITSource(DeviceAddr, MFXSTM32L152_IRQ_ERROR); +} + +/** + * @brief Clear Error global interrupt + * @param DeviceAddr: Device address on communication Bus. + * @retval None + */ +void mfxstm32l152_Error_ClearIT(uint16_t DeviceAddr) +{ + /* Clear the global Error interrupt source */ + mfxstm32l152_ClearGlobalIT(DeviceAddr, MFXSTM32L152_IRQ_ERROR); +} + +/** + * @brief get Error interrupt status + * @param DeviceAddr: Device address on communication Bus. + * @retval Error interrupts status + */ +uint8_t mfxstm32l152_Error_GetITStatus(uint16_t DeviceAddr) +{ + /* Return Error interrupt status */ + return(mfxstm32l152_GlobalITStatus(DeviceAddr, MFXSTM32L152_IRQ_ERROR)); +} + +/** + * @brief disable Error interrupt + * @param DeviceAddr: Device address on communication Bus. + * @retval None. + */ +void mfxstm32l152_Error_DisableIT(uint16_t DeviceAddr) +{ + /* Disable global Error interrupt source */ + mfxstm32l152_DisableITSource(DeviceAddr, MFXSTM32L152_IRQ_ERROR); +} + +/** + * @brief FOR DEBUG ONLY + */ +uint8_t mfxstm32l152_ReadReg(uint16_t DeviceAddr, uint8_t RegAddr) +{ + /* Get the current register value */ + return(MFX_IO_Read((uint8_t) DeviceAddr, RegAddr)); +} + +void mfxstm32l152_WriteReg(uint16_t DeviceAddr, uint8_t RegAddr, uint8_t Value) +{ + /* set the current register value */ + MFX_IO_Write((uint8_t) DeviceAddr, RegAddr, Value); +} + +/* ------------------------------------------------------------------ */ +/* ----------------------- Private functions ------------------------ */ +/* ------------------------------------------------------------------ */ +/** + * @brief Check if the device instance of the selected address is already registered + * and return its index + * @param DeviceAddr: Device address on communication Bus. + * @retval Index of the device instance if registered, 0xFF if not. + */ +static uint8_t mfxstm32l152_GetInstance(uint16_t DeviceAddr) +{ + uint8_t idx; + + /* Check all the registered instances */ + for(idx = 0; idx < MFXSTM32L152_MAX_INSTANCE ; idx ++) + { + if(mfxstm32l152[idx] == DeviceAddr) + { + return idx; + } + } + + return 0xFF; +} + +/** + * @brief Release registered device instance + * @param DeviceAddr: Device address on communication Bus. + * @retval Index of released device instance, 0xFF if not. + */ +static uint8_t mfxstm32l152_ReleaseInstance(uint16_t DeviceAddr) +{ + uint8_t idx; + + /* Check for all the registered instances */ + for(idx = 0; idx < MFXSTM32L152_MAX_INSTANCE ; idx ++) + { + if(mfxstm32l152[idx] == DeviceAddr) + { + mfxstm32l152[idx] = 0; + return idx; + } + } + return 0xFF; +} + +/** + * @brief Internal routine + * @param DeviceAddr: Device address on communication Bus. + * @param RegisterAddr: Register Address + * @param PinPosition: Pin [0:23] + * @param PinValue: 0/1 + * @retval None + */ +void mfxstm32l152_reg24_setPinValue(uint16_t DeviceAddr, uint8_t RegisterAddr, uint32_t PinPosition, uint8_t PinValue ) +{ + uint8_t tmp = 0; + uint8_t pin_0_7, pin_8_15, pin_16_23; + + pin_0_7 = PinPosition & 0x0000ff; + pin_8_15 = PinPosition >> 8; + pin_8_15 = pin_8_15 & 0x00ff; + pin_16_23 = PinPosition >> 16; + + if (pin_0_7) + { + /* Get the current register value */ + tmp = MFX_IO_Read(DeviceAddr, RegisterAddr); + + /* Set the selected pin direction */ + if (PinValue != 0) + { + tmp |= (uint8_t)pin_0_7; + } + else + { + tmp &= ~(uint8_t)pin_0_7; + } + + /* Set the new register value */ + MFX_IO_Write(DeviceAddr, RegisterAddr, tmp); + } + + if (pin_8_15) + { + /* Get the current register value */ + tmp = MFX_IO_Read(DeviceAddr, RegisterAddr+1); + + /* Set the selected pin direction */ + if (PinValue != 0) + { + tmp |= (uint8_t)pin_8_15; + } + else + { + tmp &= ~(uint8_t)pin_8_15; + } + + /* Set the new register value */ + MFX_IO_Write(DeviceAddr, RegisterAddr+1, tmp); + } + + if (pin_16_23) + { + /* Get the current register value */ + tmp = MFX_IO_Read(DeviceAddr, RegisterAddr+2); + + /* Set the selected pin direction */ + if (PinValue != 0) + { + tmp |= (uint8_t)pin_16_23; + } + else + { + tmp &= ~(uint8_t)pin_16_23; + } + + /* Set the new register value */ + MFX_IO_Write(DeviceAddr, RegisterAddr+2, tmp); + } +} + + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Drivers/BSP/Components/mfxstm32l152/mfxstm32l152.h b/Drivers/BSP/Components/mfxstm32l152/mfxstm32l152.h new file mode 100644 index 0000000..914baac --- /dev/null +++ b/Drivers/BSP/Components/mfxstm32l152/mfxstm32l152.h @@ -0,0 +1,650 @@ +/** + ****************************************************************************** + * @file mfxstm32l152.h + * @author MCD Application Team + * @brief This file contains all the functions prototypes for the + * mfxstm32l152.c IO expander driver. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2015 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MFXSTM32L152_H +#define __MFXSTM32L152_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "../Common/ts.h" +#include "../Common/io.h" +#include "../Common/idd.h" + +/** @addtogroup BSP + * @{ + */ + +/** @addtogroup Component + * @{ + */ + +/** @defgroup MFXSTM32L152 + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ + +/** @defgroup MFXSTM32L152_Exported_Types + * @{ + */ +typedef struct +{ + uint8_t SYS_CTRL; + uint8_t ERROR_SRC; + uint8_t ERROR_MSG; + uint8_t IRQ_OUT; + uint8_t IRQ_SRC_EN; + uint8_t IRQ_PENDING; + uint8_t IDD_CTRL; + uint8_t IDD_PRE_DELAY; + uint8_t IDD_SHUNT0_MSB; + uint8_t IDD_SHUNT0_LSB; + uint8_t IDD_SHUNT1_MSB; + uint8_t IDD_SHUNT1_LSB; + uint8_t IDD_SHUNT2_MSB; + uint8_t IDD_SHUNT2_LSB; + uint8_t IDD_SHUNT3_MSB; + uint8_t IDD_SHUNT3_LSB; + uint8_t IDD_SHUNT4_MSB; + uint8_t IDD_SHUNT4_LSB; + uint8_t IDD_GAIN_MSB; + uint8_t IDD_GAIN_LSB; + uint8_t IDD_VDD_MIN_MSB; + uint8_t IDD_VDD_MIN_LSB; + uint8_t IDD_VALUE_MSB; + uint8_t IDD_VALUE_MID; + uint8_t IDD_VALUE_LSB; + uint8_t IDD_CAL_OFFSET_MSB; + uint8_t IDD_CAL_OFFSET_LSB; + uint8_t IDD_SHUNT_USED; +}IDD_dbgTypeDef; + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup MFXSTM32L152_Exported_Constants + * @{ + */ + + /** + * @brief MFX COMMON defines + */ + + /** + * @brief Register address: chip IDs (R) + */ +#define MFXSTM32L152_REG_ADR_ID ((uint8_t)0x00) + /** + * @brief Register address: chip FW_VERSION (R) + */ +#define MFXSTM32L152_REG_ADR_FW_VERSION_MSB ((uint8_t)0x01) +#define MFXSTM32L152_REG_ADR_FW_VERSION_LSB ((uint8_t)0x00) + /** + * @brief Register address: System Control Register (R/W) + */ +#define MFXSTM32L152_REG_ADR_SYS_CTRL ((uint8_t)0x40) + /** + * @brief Register address: Vdd monitoring (R) + */ +#define MFXSTM32L152_REG_ADR_VDD_REF_MSB ((uint8_t)0x06) +#define MFXSTM32L152_REG_ADR_VDD_REF_LSB ((uint8_t)0x07) + /** + * @brief Register address: Error source + */ +#define MFXSTM32L152_REG_ADR_ERROR_SRC ((uint8_t)0x03) + /** + * @brief Register address: Error Message + */ +#define MFXSTM32L152_REG_ADR_ERROR_MSG ((uint8_t)0x04) + + /** + * @brief Reg Addr IRQs: to config the pin that informs Main MCU that MFX events appear + */ +#define MFXSTM32L152_REG_ADR_MFX_IRQ_OUT ((uint8_t)0x41) + /** + * @brief Reg Addr IRQs: to select the events which activate the MFXSTM32L152_IRQ_OUT signal + */ +#define MFXSTM32L152_REG_ADR_IRQ_SRC_EN ((uint8_t)0x42) + /** + * @brief Reg Addr IRQs: the Main MCU must read the IRQ_PENDING register to know the interrupt reason + */ +#define MFXSTM32L152_REG_ADR_IRQ_PENDING ((uint8_t)0x08) + /** + * @brief Reg Addr IRQs: the Main MCU must acknowledge it thanks to a writing access to the IRQ_ACK register + */ +#define MFXSTM32L152_REG_ADR_IRQ_ACK ((uint8_t)0x44) + + /** + * @brief MFXSTM32L152_REG_ADR_ID choices + */ +#define MFXSTM32L152_ID_1 ((uint8_t)0x7B) +#define MFXSTM32L152_ID_2 ((uint8_t)0x79) + + /** + * @brief MFXSTM32L152_REG_ADR_SYS_CTRL choices + */ +#define MFXSTM32L152_SWRST ((uint8_t)0x80) +#define MFXSTM32L152_STANDBY ((uint8_t)0x40) +#define MFXSTM32L152_ALTERNATE_GPIO_EN ((uint8_t)0x08) /* by the way if IDD and TS are enabled they take automatically the AF pins*/ +#define MFXSTM32L152_IDD_EN ((uint8_t)0x04) +#define MFXSTM32L152_TS_EN ((uint8_t)0x02) +#define MFXSTM32L152_GPIO_EN ((uint8_t)0x01) + + /** + * @brief MFXSTM32L152_REG_ADR_ERROR_SRC choices + */ +#define MFXSTM32L152_IDD_ERROR_SRC ((uint8_t)0x04) /* Error raised by Idd */ +#define MFXSTM32L152_TS_ERROR_SRC ((uint8_t)0x02) /* Error raised by Touch Screen */ +#define MFXSTM32L152_GPIO_ERROR_SRC ((uint8_t)0x01) /* Error raised by Gpio */ + + /** + * @brief MFXSTM32L152_REG_ADR_MFX_IRQ_OUT choices + */ +#define MFXSTM32L152_OUT_PIN_TYPE_OPENDRAIN ((uint8_t)0x00) +#define MFXSTM32L152_OUT_PIN_TYPE_PUSHPULL ((uint8_t)0x01) +#define MFXSTM32L152_OUT_PIN_POLARITY_LOW ((uint8_t)0x00) +#define MFXSTM32L152_OUT_PIN_POLARITY_HIGH ((uint8_t)0x02) + + /** + * @brief REG_ADR_IRQ_SRC_EN, REG_ADR_IRQ_PENDING & REG_ADR_IRQ_ACK choices + */ +#define MFXSTM32L152_IRQ_TS_OVF ((uint8_t)0x80) /* TouchScreen FIFO Overflow irq*/ +#define MFXSTM32L152_IRQ_TS_FULL ((uint8_t)0x40) /* TouchScreen FIFO Full irq*/ +#define MFXSTM32L152_IRQ_TS_TH ((uint8_t)0x20) /* TouchScreen FIFO threshold triggered irq*/ +#define MFXSTM32L152_IRQ_TS_NE ((uint8_t)0x10) /* TouchScreen FIFO Not Empty irq*/ +#define MFXSTM32L152_IRQ_TS_DET ((uint8_t)0x08) /* TouchScreen Detect irq*/ +#define MFXSTM32L152_IRQ_ERROR ((uint8_t)0x04) /* Error message from MFXSTM32L152 firmware irq */ +#define MFXSTM32L152_IRQ_IDD ((uint8_t)0x02) /* IDD function irq */ +#define MFXSTM32L152_IRQ_GPIO ((uint8_t)0x01) /* General GPIO irq (only for SRC_EN and PENDING) */ +#define MFXSTM32L152_IRQ_ALL ((uint8_t)0xFF) /* All global interrupts */ +#define MFXSTM32L152_IRQ_TS (MFXSTM32L152_IRQ_TS_DET | MFXSTM32L152_IRQ_TS_NE | MFXSTM32L152_IRQ_TS_TH | MFXSTM32L152_IRQ_TS_FULL | MFXSTM32L152_IRQ_TS_OVF ) + + + /** + * @brief GPIO: 24 programmable input/output called MFXSTM32L152_GPIO[23:0] are provided + */ + + /** + * @brief Reg addr: GPIO DIRECTION (R/W): GPIO pins direction: (0) input, (1) output. + */ +#define MFXSTM32L152_REG_ADR_GPIO_DIR1 ((uint8_t)0x60) /* gpio [0:7] */ +#define MFXSTM32L152_REG_ADR_GPIO_DIR2 ((uint8_t)0x61) /* gpio [8:15] */ +#define MFXSTM32L152_REG_ADR_GPIO_DIR3 ((uint8_t)0x62) /* agpio [0:7] */ + /** + * @brief Reg addr: GPIO TYPE (R/W): If GPIO in output: (0) output push pull, (1) output open drain. + * If GPIO in input: (0) input without pull resistor, (1) input with pull resistor. + */ +#define MFXSTM32L152_REG_ADR_GPIO_TYPE1 ((uint8_t)0x64) /* gpio [0:7] */ +#define MFXSTM32L152_REG_ADR_GPIO_TYPE2 ((uint8_t)0x65) /* gpio [8:15] */ +#define MFXSTM32L152_REG_ADR_GPIO_TYPE3 ((uint8_t)0x66) /* agpio [0:7] */ + /** + * @brief Reg addr: GPIO PULL_UP_PULL_DOWN (R/W): discussion open with Jean Claude + */ +#define MFXSTM32L152_REG_ADR_GPIO_PUPD1 ((uint8_t)0x68) /* gpio [0:7] */ +#define MFXSTM32L152_REG_ADR_GPIO_PUPD2 ((uint8_t)0x69) /* gpio [8:15] */ +#define MFXSTM32L152_REG_ADR_GPIO_PUPD3 ((uint8_t)0x6A) /* agpio [0:7] */ + /** + * @brief Reg addr: GPIO SET (W): When GPIO is in output mode, write (1) puts the corresponding GPO in High level. + */ +#define MFXSTM32L152_REG_ADR_GPO_SET1 ((uint8_t)0x6C) /* gpio [0:7] */ +#define MFXSTM32L152_REG_ADR_GPO_SET2 ((uint8_t)0x6D) /* gpio [8:15] */ +#define MFXSTM32L152_REG_ADR_GPO_SET3 ((uint8_t)0x6E) /* agpio [0:7] */ + /** + * @brief Reg addr: GPIO CLEAR (W): When GPIO is in output mode, write (1) puts the corresponding GPO in Low level. + */ +#define MFXSTM32L152_REG_ADR_GPO_CLR1 ((uint8_t)0x70) /* gpio [0:7] */ +#define MFXSTM32L152_REG_ADR_GPO_CLR2 ((uint8_t)0x71) /* gpio [8:15] */ +#define MFXSTM32L152_REG_ADR_GPO_CLR3 ((uint8_t)0x72) /* agpio [0:7] */ + /** + * @brief Reg addr: GPIO STATE (R): Give state of the GPIO pin. + */ +#define MFXSTM32L152_REG_ADR_GPIO_STATE1 ((uint8_t)0x10) /* gpio [0:7] */ +#define MFXSTM32L152_REG_ADR_GPIO_STATE2 ((uint8_t)0x11) /* gpio [8:15] */ +#define MFXSTM32L152_REG_ADR_GPIO_STATE3 ((uint8_t)0x12) /* agpio [0:7] */ + + /** + * @brief GPIO IRQ_GPIs + */ +/* GPIOs can INDIVIDUALLY generate interruption to the Main MCU thanks to the MFXSTM32L152_IRQ_OUT signal */ +/* the general MFXSTM32L152_IRQ_GPIO_SRC_EN shall be enabled too */ + /** + * @brief GPIO IRQ_GPI_SRC1/2/3 (R/W): registers enable or not the feature to generate irq + */ +#define MFXSTM32L152_REG_ADR_IRQ_GPI_SRC1 ((uint8_t)0x48) /* gpio [0:7] */ +#define MFXSTM32L152_REG_ADR_IRQ_GPI_SRC2 ((uint8_t)0x49) /* gpio [8:15] */ +#define MFXSTM32L152_REG_ADR_IRQ_GPI_SRC3 ((uint8_t)0x4A) /* agpio [0:7] */ + /** + * @brief GPIO IRQ_GPI_EVT1/2/3 (R/W): Irq generated on level (0) or edge (1). + */ +#define MFXSTM32L152_REG_ADR_IRQ_GPI_EVT1 ((uint8_t)0x4C) /* gpio [0:7] */ +#define MFXSTM32L152_REG_ADR_IRQ_GPI_EVT2 ((uint8_t)0x4D) /* gpio [8:15] */ +#define MFXSTM32L152_REG_ADR_IRQ_GPI_EVT3 ((uint8_t)0x4E) /* agpio [0:7] */ + /** + * @brief GPIO IRQ_GPI_TYPE1/2/3 (R/W): Irq generated on (0) : Low level or Falling edge. (1) : High level or Rising edge. + */ +#define MFXSTM32L152_REG_ADR_IRQ_GPI_TYPE1 ((uint8_t)0x50) /* gpio [0:7] */ +#define MFXSTM32L152_REG_ADR_IRQ_GPI_TYPE2 ((uint8_t)0x51) /* gpio [8:15] */ +#define MFXSTM32L152_REG_ADR_IRQ_GPI_TYPE3 ((uint8_t)0x52) /* agpio [0:7] */ + /** + * @brief GPIO IRQ_GPI_PENDING1/2/3 (R): irq occurs + */ +#define MFXSTM32L152_REG_ADR_IRQ_GPI_PENDING1 ((uint8_t)0x0C) /* gpio [0:7] */ +#define MFXSTM32L152_REG_ADR_IRQ_GPI_PENDING2 ((uint8_t)0x0D) /* gpio [8:15] */ +#define MFXSTM32L152_REG_ADR_IRQ_GPI_PENDING3 ((uint8_t)0x0E) /* agpio [0:7] */ + /** + * @brief GPIO IRQ_GPI_ACK1/2/3 (W): Write (1) to acknowledge IRQ event + */ +#define MFXSTM32L152_REG_ADR_IRQ_GPI_ACK1 ((uint8_t)0x54) /* gpio [0:7] */ +#define MFXSTM32L152_REG_ADR_IRQ_GPI_ACK2 ((uint8_t)0x55) /* gpio [8:15] */ +#define MFXSTM32L152_REG_ADR_IRQ_GPI_ACK3 ((uint8_t)0x56) /* agpio [0:7] */ + + + /** + * @brief GPIO: IO Pins definition + */ +#define MFXSTM32L152_GPIO_PIN_0 ((uint32_t)0x0001) +#define MFXSTM32L152_GPIO_PIN_1 ((uint32_t)0x0002) +#define MFXSTM32L152_GPIO_PIN_2 ((uint32_t)0x0004) +#define MFXSTM32L152_GPIO_PIN_3 ((uint32_t)0x0008) +#define MFXSTM32L152_GPIO_PIN_4 ((uint32_t)0x0010) +#define MFXSTM32L152_GPIO_PIN_5 ((uint32_t)0x0020) +#define MFXSTM32L152_GPIO_PIN_6 ((uint32_t)0x0040) +#define MFXSTM32L152_GPIO_PIN_7 ((uint32_t)0x0080) + +#define MFXSTM32L152_GPIO_PIN_8 ((uint32_t)0x0100) +#define MFXSTM32L152_GPIO_PIN_9 ((uint32_t)0x0200) +#define MFXSTM32L152_GPIO_PIN_10 ((uint32_t)0x0400) +#define MFXSTM32L152_GPIO_PIN_11 ((uint32_t)0x0800) +#define MFXSTM32L152_GPIO_PIN_12 ((uint32_t)0x1000) +#define MFXSTM32L152_GPIO_PIN_13 ((uint32_t)0x2000) +#define MFXSTM32L152_GPIO_PIN_14 ((uint32_t)0x4000) +#define MFXSTM32L152_GPIO_PIN_15 ((uint32_t)0x8000) + +#define MFXSTM32L152_GPIO_PIN_16 ((uint32_t)0x010000) +#define MFXSTM32L152_GPIO_PIN_17 ((uint32_t)0x020000) +#define MFXSTM32L152_GPIO_PIN_18 ((uint32_t)0x040000) +#define MFXSTM32L152_GPIO_PIN_19 ((uint32_t)0x080000) +#define MFXSTM32L152_GPIO_PIN_20 ((uint32_t)0x100000) +#define MFXSTM32L152_GPIO_PIN_21 ((uint32_t)0x200000) +#define MFXSTM32L152_GPIO_PIN_22 ((uint32_t)0x400000) +#define MFXSTM32L152_GPIO_PIN_23 ((uint32_t)0x800000) + +#define MFXSTM32L152_AGPIO_PIN_0 MFXSTM32L152_GPIO_PIN_16 +#define MFXSTM32L152_AGPIO_PIN_1 MFXSTM32L152_GPIO_PIN_17 +#define MFXSTM32L152_AGPIO_PIN_2 MFXSTM32L152_GPIO_PIN_18 +#define MFXSTM32L152_AGPIO_PIN_3 MFXSTM32L152_GPIO_PIN_19 +#define MFXSTM32L152_AGPIO_PIN_4 MFXSTM32L152_GPIO_PIN_20 +#define MFXSTM32L152_AGPIO_PIN_5 MFXSTM32L152_GPIO_PIN_21 +#define MFXSTM32L152_AGPIO_PIN_6 MFXSTM32L152_GPIO_PIN_22 +#define MFXSTM32L152_AGPIO_PIN_7 MFXSTM32L152_GPIO_PIN_23 + +#define MFXSTM32L152_GPIO_PINS_ALL ((uint32_t)0xFFFFFF) + + /** + * @brief GPIO: constant + */ +#define MFXSTM32L152_GPIO_DIR_IN ((uint8_t)0x0) +#define MFXSTM32L152_GPIO_DIR_OUT ((uint8_t)0x1) +#define MFXSTM32L152_IRQ_GPI_EVT_LEVEL ((uint8_t)0x0) +#define MFXSTM32L152_IRQ_GPI_EVT_EDGE ((uint8_t)0x1) +#define MFXSTM32L152_IRQ_GPI_TYPE_LLFE ((uint8_t)0x0) /* Low Level Falling Edge */ +#define MFXSTM32L152_IRQ_GPI_TYPE_HLRE ((uint8_t)0x1) /*High Level Raising Edge */ +#define MFXSTM32L152_GPI_WITHOUT_PULL_RESISTOR ((uint8_t)0x0) +#define MFXSTM32L152_GPI_WITH_PULL_RESISTOR ((uint8_t)0x1) +#define MFXSTM32L152_GPO_PUSH_PULL ((uint8_t)0x0) +#define MFXSTM32L152_GPO_OPEN_DRAIN ((uint8_t)0x1) +#define MFXSTM32L152_GPIO_PULL_DOWN ((uint8_t)0x0) +#define MFXSTM32L152_GPIO_PULL_UP ((uint8_t)0x1) + + + /** + * @brief TOUCH SCREEN Registers + */ + + /** + * @brief Touch Screen Registers + */ +#define MFXSTM32L152_TS_SETTLING ((uint8_t)0xA0) +#define MFXSTM32L152_TS_TOUCH_DET_DELAY ((uint8_t)0xA1) +#define MFXSTM32L152_TS_AVE ((uint8_t)0xA2) +#define MFXSTM32L152_TS_TRACK ((uint8_t)0xA3) +#define MFXSTM32L152_TS_FIFO_TH ((uint8_t)0xA4) +#define MFXSTM32L152_TS_FIFO_STA ((uint8_t)0x20) +#define MFXSTM32L152_TS_FIFO_LEVEL ((uint8_t)0x21) +#define MFXSTM32L152_TS_XY_DATA ((uint8_t)0x24) + + /** + * @brief TS registers masks + */ +#define MFXSTM32L152_TS_CTRL_STATUS ((uint8_t)0x08) +#define MFXSTM32L152_TS_CLEAR_FIFO ((uint8_t)0x80) + + +/** + * @brief Register address: Idd control register (R/W) + */ +#define MFXSTM32L152_REG_ADR_IDD_CTRL ((uint8_t)0x80) + +/** + * @brief Register address: Idd pre delay register (R/W) + */ +#define MFXSTM32L152_REG_ADR_IDD_PRE_DELAY ((uint8_t)0x81) + +/** + * @brief Register address: Idd Shunt registers (R/W) + */ +#define MFXSTM32L152_REG_ADR_IDD_SHUNT0_MSB ((uint8_t)0x82) +#define MFXSTM32L152_REG_ADR_IDD_SHUNT0_LSB ((uint8_t)0x83) +#define MFXSTM32L152_REG_ADR_IDD_SHUNT1_MSB ((uint8_t)0x84) +#define MFXSTM32L152_REG_ADR_IDD_SHUNT1_LSB ((uint8_t)0x85) +#define MFXSTM32L152_REG_ADR_IDD_SHUNT2_MSB ((uint8_t)0x86) +#define MFXSTM32L152_REG_ADR_IDD_SHUNT2_LSB ((uint8_t)0x87) +#define MFXSTM32L152_REG_ADR_IDD_SHUNT3_MSB ((uint8_t)0x88) +#define MFXSTM32L152_REG_ADR_IDD_SHUNT3_LSB ((uint8_t)0x89) +#define MFXSTM32L152_REG_ADR_IDD_SHUNT4_MSB ((uint8_t)0x8A) +#define MFXSTM32L152_REG_ADR_IDD_SHUNT4_LSB ((uint8_t)0x8B) + +/** + * @brief Register address: Idd ampli gain register (R/W) + */ +#define MFXSTM32L152_REG_ADR_IDD_GAIN_MSB ((uint8_t)0x8C) +#define MFXSTM32L152_REG_ADR_IDD_GAIN_LSB ((uint8_t)0x8D) + +/** + * @brief Register address: Idd VDD min register (R/W) + */ +#define MFXSTM32L152_REG_ADR_IDD_VDD_MIN_MSB ((uint8_t)0x8E) +#define MFXSTM32L152_REG_ADR_IDD_VDD_MIN_LSB ((uint8_t)0x8F) + +/** + * @brief Register address: Idd value register (R) + */ +#define MFXSTM32L152_REG_ADR_IDD_VALUE_MSB ((uint8_t)0x14) +#define MFXSTM32L152_REG_ADR_IDD_VALUE_MID ((uint8_t)0x15) +#define MFXSTM32L152_REG_ADR_IDD_VALUE_LSB ((uint8_t)0x16) + +/** + * @brief Register address: Idd calibration offset register (R) + */ +#define MFXSTM32L152_REG_ADR_IDD_CAL_OFFSET_MSB ((uint8_t)0x18) +#define MFXSTM32L152_REG_ADR_IDD_CAL_OFFSET_LSB ((uint8_t)0x19) + +/** + * @brief Register address: Idd shunt used offset register (R) + */ +#define MFXSTM32L152_REG_ADR_IDD_SHUNT_USED ((uint8_t)0x1A) + +/** + * @brief Register address: shunt stabilisation delay registers (R/W) + */ +#define MFXSTM32L152_REG_ADR_IDD_SH0_STABILIZATION ((uint8_t)0x90) +#define MFXSTM32L152_REG_ADR_IDD_SH1_STABILIZATION ((uint8_t)0x91) +#define MFXSTM32L152_REG_ADR_IDD_SH2_STABILIZATION ((uint8_t)0x92) +#define MFXSTM32L152_REG_ADR_IDD_SH3_STABILIZATION ((uint8_t)0x93) +#define MFXSTM32L152_REG_ADR_IDD_SH4_STABILIZATION ((uint8_t)0x94) + +/** + * @brief Register address: Idd number of measurements register (R/W) + */ +#define MFXSTM32L152_REG_ADR_IDD_NBR_OF_MEAS ((uint8_t)0x96) + +/** + * @brief Register address: Idd delta delay between 2 measurements register (R/W) + */ +#define MFXSTM32L152_REG_ADR_IDD_MEAS_DELTA_DELAY ((uint8_t)0x97) + +/** + * @brief Register address: Idd number of shunt on board register (R/W) + */ +#define MFXSTM32L152_REG_ADR_IDD_SHUNTS_ON_BOARD ((uint8_t)0x98) + + + +/** @defgroup IDD_Control_Register_Defines IDD Control Register Defines + * @{ + */ +/** + * @brief IDD control register masks + */ +#define MFXSTM32L152_IDD_CTRL_REQ ((uint8_t)0x01) +#define MFXSTM32L152_IDD_CTRL_SHUNT_NB ((uint8_t)0x0E) +#define MFXSTM32L152_IDD_CTRL_VREF_DIS ((uint8_t)0x40) +#define MFXSTM32L152_IDD_CTRL_CAL_DIS ((uint8_t)0x80) + +/** + * @brief IDD Shunt Number + */ +#define MFXSTM32L152_IDD_SHUNT_NB_1 ((uint8_t) 0x01) +#define MFXSTM32L152_IDD_SHUNT_NB_2 ((uint8_t) 0x02) +#define MFXSTM32L152_IDD_SHUNT_NB_3 ((uint8_t) 0x03) +#define MFXSTM32L152_IDD_SHUNT_NB_4 ((uint8_t) 0x04) +#define MFXSTM32L152_IDD_SHUNT_NB_5 ((uint8_t) 0x05) + +/** + * @brief Vref Measurement + */ +#define MFXSTM32L152_IDD_VREF_AUTO_MEASUREMENT_ENABLE ((uint8_t) 0x00) +#define MFXSTM32L152_IDD_VREF_AUTO_MEASUREMENT_DISABLE ((uint8_t) 0x70) + +/** + * @brief IDD Calibration + */ +#define MFXSTM32L152_IDD_AUTO_CALIBRATION_ENABLE ((uint8_t) 0x00) +#define MFXSTM32L152_IDD_AUTO_CALIBRATION_DISABLE ((uint8_t) 0x80) +/** + * @} + */ + +/** @defgroup IDD_PreDelay_Defines IDD PreDelay Defines + * @{ + */ +/** + * @brief IDD PreDelay masks + */ +#define MFXSTM32L152_IDD_PREDELAY_UNIT ((uint8_t) 0x80) +#define MFXSTM32L152_IDD_PREDELAY_VALUE ((uint8_t) 0x7F) + + +/** + * @brief IDD PreDelay unit + */ +#define MFXSTM32L152_IDD_PREDELAY_0_5_MS ((uint8_t) 0x00) +#define MFXSTM32L152_IDD_PREDELAY_20_MS ((uint8_t) 0x80) +/** + * @} + */ + +/** @defgroup IDD_DeltaDelay_Defines IDD Delta DElay Defines + * @{ + */ +/** + * @brief IDD Delta Delay masks + */ +#define MFXSTM32L152_IDD_DELTADELAY_UNIT ((uint8_t) 0x80) +#define MFXSTM32L152_IDD_DELTADELAY_VALUE ((uint8_t) 0x7F) + + +/** + * @brief IDD Delta Delay unit + */ +#define MFXSTM32L152_IDD_DELTADELAY_0_5_MS ((uint8_t) 0x00) +#define MFXSTM32L152_IDD_DELTADELAY_20_MS ((uint8_t) 0x80) + + +/** + * @} + */ + +/** + * @} + */ + + +/* Exported macro ------------------------------------------------------------*/ + +/** @defgroup MFXSTM32L152_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup MFXSTM32L152_Exported_Functions + * @{ + */ + +/** + * @brief MFXSTM32L152 Control functions + */ +void mfxstm32l152_Init(uint16_t DeviceAddr); +void mfxstm32l152_DeInit(uint16_t DeviceAddr); +void mfxstm32l152_Reset(uint16_t DeviceAddr); +uint16_t mfxstm32l152_ReadID(uint16_t DeviceAddr); +uint16_t mfxstm32l152_ReadFwVersion(uint16_t DeviceAddr); +void mfxstm32l152_LowPower(uint16_t DeviceAddr); +void mfxstm32l152_WakeUp(uint16_t DeviceAddr); + +void mfxstm32l152_EnableITSource(uint16_t DeviceAddr, uint8_t Source); +void mfxstm32l152_DisableITSource(uint16_t DeviceAddr, uint8_t Source); +uint8_t mfxstm32l152_GlobalITStatus(uint16_t DeviceAddr, uint8_t Source); +void mfxstm32l152_ClearGlobalIT(uint16_t DeviceAddr, uint8_t Source); + +void mfxstm32l152_SetIrqOutPinPolarity(uint16_t DeviceAddr, uint8_t Polarity); +void mfxstm32l152_SetIrqOutPinType(uint16_t DeviceAddr, uint8_t Type); + + +/** + * @brief MFXSTM32L152 IO functionalities functions + */ +void mfxstm32l152_IO_Start(uint16_t DeviceAddr, uint32_t IO_Pin); +uint8_t mfxstm32l152_IO_Config(uint16_t DeviceAddr, uint32_t IO_Pin, IO_ModeTypedef IO_Mode); +void mfxstm32l152_IO_WritePin(uint16_t DeviceAddr, uint32_t IO_Pin, uint8_t PinState); +uint32_t mfxstm32l152_IO_ReadPin(uint16_t DeviceAddr, uint32_t IO_Pin); +void mfxstm32l152_IO_EnableIT(uint16_t DeviceAddr); +void mfxstm32l152_IO_DisableIT(uint16_t DeviceAddr); +uint32_t mfxstm32l152_IO_ITStatus(uint16_t DeviceAddr, uint32_t IO_Pin); +void mfxstm32l152_IO_ClearIT(uint16_t DeviceAddr, uint32_t IO_Pin); + +void mfxstm32l152_IO_InitPin(uint16_t DeviceAddr, uint32_t IO_Pin, uint8_t Direction); +void mfxstm32l152_IO_EnableAF(uint16_t DeviceAddr); +void mfxstm32l152_IO_DisableAF(uint16_t DeviceAddr); +void mfxstm32l152_IO_SetIrqTypeMode(uint16_t DeviceAddr, uint32_t IO_Pin, uint8_t Type); +void mfxstm32l152_IO_SetIrqEvtMode(uint16_t DeviceAddr, uint32_t IO_Pin, uint8_t Evt); +void mfxstm32l152_IO_EnablePinIT(uint16_t DeviceAddr, uint32_t IO_Pin); +void mfxstm32l152_IO_DisablePinIT(uint16_t DeviceAddr, uint32_t IO_Pin); + +/** + * @brief MFXSTM32L152 Touch screen functionalities functions + */ +void mfxstm32l152_TS_Start(uint16_t DeviceAddr); +uint8_t mfxstm32l152_TS_DetectTouch(uint16_t DeviceAddr); +void mfxstm32l152_TS_GetXY(uint16_t DeviceAddr, uint16_t *X, uint16_t *Y); +void mfxstm32l152_TS_EnableIT(uint16_t DeviceAddr); +void mfxstm32l152_TS_DisableIT(uint16_t DeviceAddr); +uint8_t mfxstm32l152_TS_ITStatus (uint16_t DeviceAddr); +void mfxstm32l152_TS_ClearIT (uint16_t DeviceAddr); + +/** + * @brief MFXSTM32L152 IDD current measurement functionalities functions + */ +void mfxstm32l152_IDD_Start(uint16_t DeviceAddr); +void mfxstm32l152_IDD_Config(uint16_t DeviceAddr, IDD_ConfigTypeDef MfxIddConfig); +void mfxstm32l152_IDD_ConfigShuntNbLimit(uint16_t DeviceAddr, uint8_t ShuntNbLimit); +void mfxstm32l152_IDD_GetValue(uint16_t DeviceAddr, uint32_t *ReadValue); +uint8_t mfxstm32l152_IDD_GetShuntUsed(uint16_t DeviceAddr); +void mfxstm32l152_IDD_EnableIT(uint16_t DeviceAddr); +void mfxstm32l152_IDD_ClearIT(uint16_t DeviceAddr); +uint8_t mfxstm32l152_IDD_GetITStatus(uint16_t DeviceAddr); +void mfxstm32l152_IDD_DisableIT(uint16_t DeviceAddr); + +/** + * @brief MFXSTM32L152 Error management functions + */ +uint8_t mfxstm32l152_Error_ReadSrc(uint16_t DeviceAddr); +uint8_t mfxstm32l152_Error_ReadMsg(uint16_t DeviceAddr); +void mfxstm32l152_Error_EnableIT(uint16_t DeviceAddr); +void mfxstm32l152_Error_ClearIT(uint16_t DeviceAddr); +uint8_t mfxstm32l152_Error_GetITStatus(uint16_t DeviceAddr); +void mfxstm32l152_Error_DisableIT(uint16_t DeviceAddr); + +uint8_t mfxstm32l152_ReadReg(uint16_t DeviceAddr, uint8_t RegAddr); +void mfxstm32l152_WriteReg(uint16_t DeviceAddr, uint8_t RegAddr, uint8_t Value); + + + +/** + * @brief iobus prototypes (they should be defined in common/stm32_iobus.h) + */ +void MFX_IO_Init(void); +void MFX_IO_DeInit(void); +void MFX_IO_ITConfig (void); +void MFX_IO_EnableWakeupPin(void); +void MFX_IO_Wakeup(void); +void MFX_IO_Delay(uint32_t delay); +void MFX_IO_Write(uint16_t addr, uint8_t reg, uint8_t value); +uint8_t MFX_IO_Read(uint16_t addr, uint8_t reg); +uint16_t MFX_IO_ReadMultiple(uint16_t addr, uint8_t reg, uint8_t *buffer, uint16_t length); + +/** + * @} + */ + +/* Touch screen driver structure */ +extern TS_DrvTypeDef mfxstm32l152_ts_drv; + +/* IO driver structure */ +extern IO_DrvTypeDef mfxstm32l152_io_drv; + +/* IDD driver structure */ +extern IDD_DrvTypeDef mfxstm32l152_idd_drv; + + +#ifdef __cplusplus +} +#endif +#endif /* __MFXSTM32L152_H */ + + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/