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358 lines
11 KiB
358 lines
11 KiB
/** |
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****************************************************************************** |
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* @file stm32l496g_discovery_sram.c |
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* @author MCD Application Team |
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* @brief This file provides a set of functions needed to drive the |
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* IS66WV51216EBLL SRAM memory mounted on STM32L496G-Discovery board. |
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@verbatim |
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============================================================================== |
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##### How to use this driver ##### |
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============================================================================== |
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[..] |
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(#) This driver is used to drive the IS66WV51216EBLL-70BLI SRAM external memory mounted |
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on STM32L496G-Discovery evaluation board. |
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(#) This driver does not need a specific component driver for the SRAM device |
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to be included with. |
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(#) Initialization steps: |
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(++) Initialize the SRAM external memory using the BSP_SRAM_Init() function. This |
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function includes the MSP layer hardware resources initialization and the |
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FMC controller configuration to interface with the external SRAM memory. |
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(#) SRAM read/write operations |
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(++) SRAM external memory can be accessed with read/write operations once it is |
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initialized. |
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Read/write operation can be performed with AHB access using the functions |
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BSP_SRAM_ReadData()/BSP_SRAM_WriteData(), or by DMA transfer using the functions |
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BSP_SRAM_ReadData_DMA()/BSP_SRAM_WriteData_DMA(). |
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(++) The AHB access is performed with 16-bit width transaction, the DMA transfer |
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configuration is fixed at single (no burst) halfword transfer |
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(see the SRAM_MspInit() static function). |
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(++) User can implement his own functions for read/write access with his desired |
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configurations. |
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(++) If interrupt mode is used for DMA transfer, the function BSP_SRAM_DMA_IRQHandler() |
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is called in IRQ handler file, to serve the generated interrupt once the DMA |
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transfer is complete. |
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@endverbatim |
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****************************************************************************** |
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* @attention |
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* |
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* <h2><center>© Copyright (c) 2017 STMicroelectronics. |
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* All rights reserved.</center></h2> |
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* |
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* This software component is licensed by ST under BSD 3-Clause license, |
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* the "License"; You may not use this file except in compliance with the |
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* License. You may obtain a copy of the License at: |
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* opensource.org/licenses/BSD-3-Clause |
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* |
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****************************************************************************** |
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*/ |
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/* Includes ------------------------------------------------------------------*/ |
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#include "stm32l496g_discovery_sram.h" |
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/** @addtogroup BSP |
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* @{ |
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*/ |
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/** @addtogroup STM32L496G_DISCOVERY |
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* @{ |
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*/ |
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/** @defgroup STM32L496G_DISCOVERY_SRAM STM32L496G-DISCOVERY SRAM |
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* @{ |
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*/ |
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/* Private variables ---------------------------------------------------------*/ |
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/** @defgroup STM32L496G_DISCOVERY_SRAM_Private_Variables Private Variables |
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* @{ |
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*/ |
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static SRAM_HandleTypeDef sramHandle; |
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static FMC_NORSRAM_TimingTypeDef Timing; |
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/** |
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* @} |
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*/ |
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/* Private macros ------------------------------------------------------------*/ |
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/* Private constants ---------------------------------------------------------*/ |
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/** @defgroup STM32L496G_DISCOVERY_SRAM_Private_Constants Private Constants |
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* @{ |
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*/ |
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/* Timings for SRAM IS66WV51216EBLL-70BLI */ |
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#define SRAM_ADDR_SETUP_TIME 5 /* 60ns with a clock at 80 MHz (period of 12.5 ns) */ |
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#define SRAM_DATA_SETUP_TIME 3 /* 30ns with a clock at 80 MHz (period of 12.5 ns) */ |
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#define SRAM_TURN_AROUND_TIME 1 /* 5ns with a clock at 80 MHz (perido of 12.5 ns) */ |
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/** |
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* @} |
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*/ |
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/* Private function prototypes -----------------------------------------------*/ |
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/** @defgroup STM32L496G_DISCOVERY_SRAM_Private_Functions Private Functions |
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* @{ |
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*/ |
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static void SRAM_MspInit(void); |
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/** |
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* @} |
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*/ |
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/* Private functions ---------------------------------------------------------*/ |
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/** @defgroup STM32L496G_DISCOVERY_SRAM_Exported_Functions Exported Functions |
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* @{ |
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*/ |
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/** |
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* @brief Initializes the SRAM device. |
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* @retval SRAM status |
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*/ |
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uint8_t BSP_SRAM_Init(void) |
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{ |
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sramHandle.Instance = FMC_NORSRAM_DEVICE; |
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sramHandle.Extended = FMC_NORSRAM_EXTENDED_DEVICE; |
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/* SRAM device configuration */ |
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Timing.AddressSetupTime = SRAM_ADDR_SETUP_TIME; |
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Timing.DataSetupTime = SRAM_DATA_SETUP_TIME; |
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Timing.BusTurnAroundDuration = SRAM_TURN_AROUND_TIME; |
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Timing.AccessMode = FMC_ACCESS_MODE_A; |
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sramHandle.Init.NSBank = FMC_NORSRAM_BANK2; |
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sramHandle.Init.DataAddressMux = FMC_DATA_ADDRESS_MUX_DISABLE; |
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sramHandle.Init.MemoryType = FMC_MEMORY_TYPE_SRAM; |
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sramHandle.Init.MemoryDataWidth = FMC_NORSRAM_MEM_BUS_WIDTH_16; |
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sramHandle.Init.BurstAccessMode = FMC_BURST_ACCESS_MODE_DISABLE; |
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sramHandle.Init.WriteOperation = FMC_WRITE_OPERATION_ENABLE; |
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sramHandle.Init.ExtendedMode = FMC_EXTENDED_MODE_DISABLE; |
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sramHandle.Init.AsynchronousWait = FMC_ASYNCHRONOUS_WAIT_DISABLE; |
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sramHandle.Init.WriteBurst = FMC_WRITE_BURST_DISABLE; |
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sramHandle.Init.ContinuousClock = FMC_CONTINUOUS_CLOCK_SYNC_ONLY; |
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sramHandle.Init.WriteFifo = FMC_WRITE_FIFO_DISABLE; |
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sramHandle.Init.PageSize = FMC_PAGE_SIZE_NONE; |
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/* SRAM controller initialization */ |
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SRAM_MspInit(); |
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if (HAL_SRAM_Init(&sramHandle, &Timing, &Timing) != HAL_OK) |
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{ |
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return SRAM_ERROR; |
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} |
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else |
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{ |
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return SRAM_OK; |
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} |
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} |
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/** |
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* @brief Reads an amount of data from the SRAM device in polling mode. |
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* @param uwStartAddress: Read start address |
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* @param pData: Pointer to data to be read |
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* @param uwDataSize: Size of read data from the memory |
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* @retval SRAM status |
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*/ |
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uint8_t BSP_SRAM_ReadData(uint32_t uwStartAddress, uint16_t *pData, uint32_t uwDataSize) |
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{ |
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if (HAL_SRAM_Read_16b(&sramHandle, (uint32_t *)uwStartAddress, pData, uwDataSize) != HAL_OK) |
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{ |
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return SRAM_ERROR; |
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} |
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else |
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{ |
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return SRAM_OK; |
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} |
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} |
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/** |
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* @brief Reads an amount of data from the SRAM device in DMA mode. |
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* @param uwStartAddress: Read start address |
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* @param pData: Pointer to data to be read |
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* @param uwDataSize: Size of read data from the memory |
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* @retval SRAM status |
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*/ |
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uint8_t BSP_SRAM_ReadData_DMA(uint32_t uwStartAddress, uint16_t *pData, uint32_t uwDataSize) |
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{ |
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if (HAL_SRAM_Read_DMA(&sramHandle, (uint32_t *)uwStartAddress, (uint32_t *)pData, uwDataSize) != HAL_OK) |
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{ |
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return SRAM_ERROR; |
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} |
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else |
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{ |
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return SRAM_OK; |
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} |
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} |
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/** |
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* @brief Writes an amount of data from the SRAM device in polling mode. |
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* @param uwStartAddress: Write start address |
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* @param pData: Pointer to data to be written |
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* @param uwDataSize: Size of written data from the memory |
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* @retval SRAM status |
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*/ |
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uint8_t BSP_SRAM_WriteData(uint32_t uwStartAddress, uint16_t *pData, uint32_t uwDataSize) |
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{ |
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if (HAL_SRAM_Write_16b(&sramHandle, (uint32_t *)uwStartAddress, pData, uwDataSize) != HAL_OK) |
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{ |
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return SRAM_ERROR; |
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} |
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else |
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{ |
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return SRAM_OK; |
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} |
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} |
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/** |
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* @brief Writes an amount of data from the SRAM device in DMA mode. |
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* @param uwStartAddress: Write start address |
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* @param pData: Pointer to data to be written |
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* @param uwDataSize: Size of written data from the memory |
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* @retval SRAM status |
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*/ |
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uint8_t BSP_SRAM_WriteData_DMA(uint32_t uwStartAddress, uint16_t *pData, uint32_t uwDataSize) |
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{ |
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if (HAL_SRAM_Write_DMA(&sramHandle, (uint32_t *)uwStartAddress, (uint32_t *)pData, uwDataSize) != HAL_OK) |
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{ |
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return SRAM_ERROR; |
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} |
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else |
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{ |
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return SRAM_OK; |
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} |
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} |
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/** |
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* @brief Handles SRAM DMA transfer interrupt request. |
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* @retval None |
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*/ |
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void BSP_SRAM_DMA_IRQHandler(void) |
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{ |
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HAL_DMA_IRQHandler(sramHandle.hdma); |
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} |
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/** @addtogroup STM32L476G_EVAL_SRAM_Private_Functions |
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* @{ |
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*/ |
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/** |
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* @brief Initializes SRAM MSP. |
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* @retval None |
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*/ |
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static void SRAM_MspInit(void) |
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{ |
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static DMA_HandleTypeDef dmaHandle; |
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GPIO_InitTypeDef gpioinitstruct; |
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SRAM_HandleTypeDef *hsram = &sramHandle; |
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/* Enable FMC clock */ |
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__HAL_RCC_FMC_CLK_ENABLE(); |
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/* Enable chosen DMAx clock */ |
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SRAM_DMAx_CLK_ENABLE(); |
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/* Enable GPIOs clock */ |
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__HAL_RCC_GPIOD_CLK_ENABLE(); |
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__HAL_RCC_GPIOE_CLK_ENABLE(); |
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__HAL_RCC_GPIOF_CLK_ENABLE(); |
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__HAL_RCC_GPIOG_CLK_ENABLE(); |
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__HAL_RCC_PWR_CLK_ENABLE(); |
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HAL_PWREx_EnableVddIO2(); |
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/* Common GPIO configuration */ |
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gpioinitstruct.Mode = GPIO_MODE_AF_PP; |
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gpioinitstruct.Pull = GPIO_NOPULL; |
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gpioinitstruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; |
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gpioinitstruct.Alternate = GPIO_AF12_FMC; |
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/*## Data Bus #######*/ |
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/* GPIOD configuration */ |
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gpioinitstruct.Pin = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_8 | GPIO_PIN_9 | |
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GPIO_PIN_10 | GPIO_PIN_14 | GPIO_PIN_15; |
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HAL_GPIO_Init(GPIOD, &gpioinitstruct); |
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/* GPIOE configuration */ |
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gpioinitstruct.Pin = GPIO_PIN_7 | GPIO_PIN_8 | GPIO_PIN_9 | GPIO_PIN_10 | |
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GPIO_PIN_11 | GPIO_PIN_12 | GPIO_PIN_13 | |
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GPIO_PIN_14 | GPIO_PIN_15; |
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HAL_GPIO_Init(GPIOE, &gpioinitstruct); |
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/*## Address Bus #######*/ |
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/* GPIOD configuration */ |
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gpioinitstruct.Pin = GPIO_PIN_11 | GPIO_PIN_12 | GPIO_PIN_13; |
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HAL_GPIO_Init(GPIOD, &gpioinitstruct); |
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/* GPIOF configuration */ |
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gpioinitstruct.Pin = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_3 | |
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GPIO_PIN_4 | GPIO_PIN_5 | GPIO_PIN_12 | GPIO_PIN_13 | |
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GPIO_PIN_14 | GPIO_PIN_15; |
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HAL_GPIO_Init(GPIOF, &gpioinitstruct); |
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/* GPIOG configuration */ |
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gpioinitstruct.Pin = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2 | |
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GPIO_PIN_3 | GPIO_PIN_4 | GPIO_PIN_5; |
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HAL_GPIO_Init(GPIOG, &gpioinitstruct); |
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/*## NOE and NWE configuration #######*/ |
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gpioinitstruct.Pull = GPIO_PULLUP; |
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gpioinitstruct.Pin = GPIO_PIN_4 | GPIO_PIN_5; |
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HAL_GPIO_Init(GPIOD, &gpioinitstruct); |
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HAL_Delay(1); |
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/*## NBL0, NBL1 configuration #######*/ |
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gpioinitstruct.Pin = GPIO_PIN_0 | GPIO_PIN_1; |
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HAL_GPIO_Init(GPIOE, &gpioinitstruct); |
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/*## NE configuration #######*/ |
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gpioinitstruct.Pin = GPIO_PIN_9; |
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HAL_GPIO_Init(GPIOG, &gpioinitstruct); |
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/* Configure common DMA parameters */ |
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dmaHandle.Init.Direction = DMA_MEMORY_TO_MEMORY; |
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dmaHandle.Init.PeriphInc = DMA_PINC_ENABLE; |
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dmaHandle.Init.MemInc = DMA_MINC_ENABLE; |
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dmaHandle.Init.PeriphDataAlignment = DMA_PDATAALIGN_HALFWORD; |
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dmaHandle.Init.MemDataAlignment = DMA_MDATAALIGN_HALFWORD; |
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dmaHandle.Init.Mode = DMA_NORMAL; |
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dmaHandle.Init.Priority = DMA_PRIORITY_HIGH; |
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dmaHandle.Instance = SRAM_DMAx_CHANNEL; |
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/* Associate the DMA handle */ |
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__HAL_LINKDMA(hsram, hdma, dmaHandle); |
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/* Deinitialize the Stream for new transfer */ |
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HAL_DMA_DeInit(&dmaHandle); |
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/* Configure the DMA Stream */ |
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HAL_DMA_Init(&dmaHandle); |
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/* NVIC configuration for DMA transfer complete interrupt */ |
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HAL_NVIC_SetPriority(SRAM_DMAx_IRQn, 5, 0); |
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HAL_NVIC_EnableIRQ(SRAM_DMAx_IRQn); |
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} |
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/** |
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* @} |
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*/ |
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/** |
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* @} |
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*/ |
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/** |
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* @} |
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*/ |
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/** |
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* @} |
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*/ |
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/** |
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* @} |
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*/ |
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/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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