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1316 lines
47 KiB
1316 lines
47 KiB
/** |
|
****************************************************************************** |
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* @file stm32l4xx_hal_flash_ex.c |
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* @author MCD Application Team |
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* @brief Extended FLASH HAL module driver. |
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* This file provides firmware functions to manage the following |
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* functionalities of the FLASH extended peripheral: |
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* + Extended programming operations functions |
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* |
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@verbatim |
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============================================================================== |
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##### Flash Extended features ##### |
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============================================================================== |
|
|
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[..] Comparing to other previous devices, the FLASH interface for STM32L4xx |
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devices contains the following additional features |
|
|
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(+) Capacity up to 2 Mbyte with dual bank architecture supporting read-while-write |
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capability (RWW) |
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(+) Dual bank memory organization |
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(+) PCROP protection for all banks |
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|
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##### How to use this driver ##### |
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============================================================================== |
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[..] This driver provides functions to configure and program the FLASH memory |
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of all STM32L4xx devices. It includes |
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(#) Flash Memory Erase functions: |
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(++) Lock and Unlock the FLASH interface using HAL_FLASH_Unlock() and |
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HAL_FLASH_Lock() functions |
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(++) Erase function: Erase page, erase all sectors |
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(++) There are two modes of erase : |
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(+++) Polling Mode using HAL_FLASHEx_Erase() |
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(+++) Interrupt Mode using HAL_FLASHEx_Erase_IT() |
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|
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(#) Option Bytes Programming function: Use HAL_FLASHEx_OBProgram() to : |
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(++) Set/Reset the write protection |
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(++) Set the Read protection Level |
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(++) Program the user Option Bytes |
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(++) Configure the PCROP protection |
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|
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(#) Get Option Bytes Configuration function: Use HAL_FLASHEx_OBGetConfig() to : |
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(++) Get the value of a write protection area |
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(++) Know if the read protection is activated |
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(++) Get the value of the user Option Bytes |
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(++) Get the value of a PCROP area |
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|
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@endverbatim |
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****************************************************************************** |
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* @attention |
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* |
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* Copyright (c) 2017 STMicroelectronics. |
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* All rights reserved. |
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* |
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* This software is licensed under terms that can be found in the LICENSE file in |
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* the root directory of this software component. |
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* If no LICENSE file comes with this software, it is provided AS-IS. |
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****************************************************************************** |
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*/ |
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|
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/* Includes ------------------------------------------------------------------*/ |
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#include "stm32l4xx_hal.h" |
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|
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/** @addtogroup STM32L4xx_HAL_Driver |
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* @{ |
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*/ |
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|
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/** @defgroup FLASHEx FLASHEx |
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* @brief FLASH Extended HAL module driver |
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* @{ |
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*/ |
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|
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#ifdef HAL_FLASH_MODULE_ENABLED |
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|
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/* Private typedef -----------------------------------------------------------*/ |
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/* Private define ------------------------------------------------------------*/ |
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/* Private macro -------------------------------------------------------------*/ |
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/* Private variables ---------------------------------------------------------*/ |
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/* Private function prototypes -----------------------------------------------*/ |
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/** @defgroup FLASHEx_Private_Functions FLASHEx Private Functions |
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* @{ |
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*/ |
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static void FLASH_MassErase(uint32_t Banks); |
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static HAL_StatusTypeDef FLASH_OB_WRPConfig(uint32_t WRPArea, uint32_t WRPStartOffset, uint32_t WRDPEndOffset); |
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static HAL_StatusTypeDef FLASH_OB_RDPConfig(uint32_t RDPLevel); |
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static HAL_StatusTypeDef FLASH_OB_UserConfig(uint32_t UserType, uint32_t UserConfig); |
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static HAL_StatusTypeDef FLASH_OB_PCROPConfig(uint32_t PCROPConfig, uint32_t PCROPStartAddr, uint32_t PCROPEndAddr); |
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static void FLASH_OB_GetWRP(uint32_t WRPArea, uint32_t * WRPStartOffset, uint32_t * WRDPEndOffset); |
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static uint32_t FLASH_OB_GetRDP(void); |
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static uint32_t FLASH_OB_GetUser(void); |
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static void FLASH_OB_GetPCROP(uint32_t * PCROPConfig, uint32_t * PCROPStartAddr, uint32_t * PCROPEndAddr); |
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/** |
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* @} |
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*/ |
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|
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/* Exported functions -------------------------------------------------------*/ |
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/** @defgroup FLASHEx_Exported_Functions FLASHEx Exported Functions |
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* @{ |
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*/ |
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|
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/** @defgroup FLASHEx_Exported_Functions_Group1 Extended IO operation functions |
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* @brief Extended IO operation functions |
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* |
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@verbatim |
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=============================================================================== |
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##### Extended programming operation functions ##### |
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=============================================================================== |
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[..] |
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This subsection provides a set of functions allowing to manage the Extended FLASH |
|
programming operations Operations. |
|
|
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@endverbatim |
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* @{ |
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*/ |
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/** |
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* @brief Perform a mass erase or erase the specified FLASH memory pages. |
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* @param[in] pEraseInit: pointer to an FLASH_EraseInitTypeDef structure that |
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* contains the configuration information for the erasing. |
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* |
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* @param[out] PageError : pointer to variable that contains the configuration |
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* information on faulty page in case of error (0xFFFFFFFF means that all |
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* the pages have been correctly erased) |
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* |
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* @retval HAL Status |
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*/ |
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HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *PageError) |
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{ |
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HAL_StatusTypeDef status; |
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uint32_t page_index; |
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|
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/* Process Locked */ |
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__HAL_LOCK(&pFlash); |
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|
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/* Check the parameters */ |
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assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase)); |
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|
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/* Wait for last operation to be completed */ |
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status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); |
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|
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if (status == HAL_OK) |
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{ |
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pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; |
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|
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/* Deactivate the cache if they are activated to avoid data misbehavior */ |
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if(READ_BIT(FLASH->ACR, FLASH_ACR_ICEN) != 0U) |
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{ |
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if(READ_BIT(FLASH->ACR, FLASH_ACR_DCEN) != 0U) |
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{ |
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/* Disable data cache */ |
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__HAL_FLASH_DATA_CACHE_DISABLE(); |
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pFlash.CacheToReactivate = FLASH_CACHE_ICACHE_DCACHE_ENABLED; |
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} |
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else |
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{ |
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pFlash.CacheToReactivate = FLASH_CACHE_ICACHE_ENABLED; |
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} |
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} |
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else if(READ_BIT(FLASH->ACR, FLASH_ACR_DCEN) != 0U) |
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{ |
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/* Disable data cache */ |
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__HAL_FLASH_DATA_CACHE_DISABLE(); |
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pFlash.CacheToReactivate = FLASH_CACHE_DCACHE_ENABLED; |
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} |
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else |
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{ |
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pFlash.CacheToReactivate = FLASH_CACHE_DISABLED; |
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} |
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|
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if (pEraseInit->TypeErase == FLASH_TYPEERASE_MASSERASE) |
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{ |
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/* Mass erase to be done */ |
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FLASH_MassErase(pEraseInit->Banks); |
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|
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/* Wait for last operation to be completed */ |
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status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); |
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|
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#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ |
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defined (STM32L496xx) || defined (STM32L4A6xx) || \ |
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defined (STM32L4P5xx) || defined (STM32L4Q5xx) || \ |
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defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) |
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/* If the erase operation is completed, disable the MER1 and MER2 Bits */ |
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CLEAR_BIT(FLASH->CR, (FLASH_CR_MER1 | FLASH_CR_MER2)); |
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#else |
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/* If the erase operation is completed, disable the MER1 Bit */ |
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CLEAR_BIT(FLASH->CR, (FLASH_CR_MER1)); |
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#endif |
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} |
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else |
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{ |
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/*Initialization of PageError variable*/ |
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*PageError = 0xFFFFFFFFU; |
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|
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for(page_index = pEraseInit->Page; page_index < (pEraseInit->Page + pEraseInit->NbPages); page_index++) |
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{ |
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FLASH_PageErase(page_index, pEraseInit->Banks); |
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|
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/* Wait for last operation to be completed */ |
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status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); |
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|
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/* If the erase operation is completed, disable the PER Bit */ |
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CLEAR_BIT(FLASH->CR, (FLASH_CR_PER | FLASH_CR_PNB)); |
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|
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if (status != HAL_OK) |
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{ |
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/* In case of error, stop erase procedure and return the faulty address */ |
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*PageError = page_index; |
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break; |
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} |
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} |
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} |
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|
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/* Flush the caches to be sure of the data consistency */ |
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FLASH_FlushCaches(); |
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} |
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|
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/* Process Unlocked */ |
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__HAL_UNLOCK(&pFlash); |
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|
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return status; |
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} |
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|
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/** |
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* @brief Perform a mass erase or erase the specified FLASH memory pages with interrupt enabled. |
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* @param pEraseInit pointer to an FLASH_EraseInitTypeDef structure that |
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* contains the configuration information for the erasing. |
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* |
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* @retval HAL Status |
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*/ |
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HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit) |
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{ |
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HAL_StatusTypeDef status = HAL_OK; |
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|
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/* Process Locked */ |
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__HAL_LOCK(&pFlash); |
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|
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/* Check the parameters */ |
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assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase)); |
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|
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pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; |
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|
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/* Deactivate the cache if they are activated to avoid data misbehavior */ |
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if(READ_BIT(FLASH->ACR, FLASH_ACR_ICEN) != 0U) |
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{ |
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if(READ_BIT(FLASH->ACR, FLASH_ACR_DCEN) != 0U) |
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{ |
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/* Disable data cache */ |
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__HAL_FLASH_DATA_CACHE_DISABLE(); |
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pFlash.CacheToReactivate = FLASH_CACHE_ICACHE_DCACHE_ENABLED; |
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} |
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else |
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{ |
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pFlash.CacheToReactivate = FLASH_CACHE_ICACHE_ENABLED; |
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} |
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} |
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else if(READ_BIT(FLASH->ACR, FLASH_ACR_DCEN) != 0U) |
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{ |
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/* Disable data cache */ |
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__HAL_FLASH_DATA_CACHE_DISABLE(); |
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pFlash.CacheToReactivate = FLASH_CACHE_DCACHE_ENABLED; |
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} |
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else |
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{ |
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pFlash.CacheToReactivate = FLASH_CACHE_DISABLED; |
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} |
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/* Enable End of Operation and Error interrupts */ |
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__HAL_FLASH_ENABLE_IT(FLASH_IT_EOP | FLASH_IT_OPERR); |
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pFlash.Bank = pEraseInit->Banks; |
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if (pEraseInit->TypeErase == FLASH_TYPEERASE_MASSERASE) |
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{ |
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/* Mass erase to be done */ |
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pFlash.ProcedureOnGoing = FLASH_PROC_MASS_ERASE; |
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FLASH_MassErase(pEraseInit->Banks); |
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} |
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else |
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{ |
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/* Erase by page to be done */ |
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pFlash.ProcedureOnGoing = FLASH_PROC_PAGE_ERASE; |
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pFlash.NbPagesToErase = pEraseInit->NbPages; |
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pFlash.Page = pEraseInit->Page; |
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|
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/*Erase 1st page and wait for IT */ |
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FLASH_PageErase(pEraseInit->Page, pEraseInit->Banks); |
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} |
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return status; |
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} |
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|
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/** |
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* @brief Program Option bytes. |
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* @param pOBInit pointer to an FLASH_OBInitStruct structure that |
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* contains the configuration information for the programming. |
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* |
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* @retval HAL Status |
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*/ |
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HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit) |
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{ |
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HAL_StatusTypeDef status = HAL_OK; |
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/* Process Locked */ |
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__HAL_LOCK(&pFlash); |
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|
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/* Check the parameters */ |
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assert_param(IS_OPTIONBYTE(pOBInit->OptionType)); |
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pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; |
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|
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/* Write protection configuration */ |
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if((pOBInit->OptionType & OPTIONBYTE_WRP) != 0U) |
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{ |
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/* Configure of Write protection on the selected area */ |
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if(FLASH_OB_WRPConfig(pOBInit->WRPArea, pOBInit->WRPStartOffset, pOBInit->WRPEndOffset) != HAL_OK) |
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{ |
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status = HAL_ERROR; |
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} |
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|
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} |
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/* Read protection configuration */ |
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if((pOBInit->OptionType & OPTIONBYTE_RDP) != 0U) |
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{ |
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/* Configure the Read protection level */ |
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if(FLASH_OB_RDPConfig(pOBInit->RDPLevel) != HAL_OK) |
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{ |
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status = HAL_ERROR; |
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} |
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} |
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|
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/* User Configuration */ |
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if((pOBInit->OptionType & OPTIONBYTE_USER) != 0U) |
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{ |
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/* Configure the user option bytes */ |
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if(FLASH_OB_UserConfig(pOBInit->USERType, pOBInit->USERConfig) != HAL_OK) |
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{ |
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status = HAL_ERROR; |
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} |
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} |
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|
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/* PCROP Configuration */ |
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if((pOBInit->OptionType & OPTIONBYTE_PCROP) != 0U) |
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{ |
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if (pOBInit->PCROPStartAddr != pOBInit->PCROPEndAddr) |
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{ |
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/* Configure the Proprietary code readout protection */ |
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if(FLASH_OB_PCROPConfig(pOBInit->PCROPConfig, pOBInit->PCROPStartAddr, pOBInit->PCROPEndAddr) != HAL_OK) |
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{ |
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status = HAL_ERROR; |
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} |
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} |
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} |
|
|
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/* Process Unlocked */ |
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__HAL_UNLOCK(&pFlash); |
|
|
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return status; |
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} |
|
|
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/** |
|
* @brief Get the Option bytes configuration. |
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* @param pOBInit pointer to an FLASH_OBInitStruct structure that contains the |
|
* configuration information. |
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* @note The fields pOBInit->WRPArea and pOBInit->PCROPConfig should indicate |
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* which area is requested for the WRP and PCROP, else no information will be returned |
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* |
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* @retval None |
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*/ |
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void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit) |
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{ |
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pOBInit->OptionType = (OPTIONBYTE_RDP | OPTIONBYTE_USER); |
|
|
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#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ |
|
defined (STM32L496xx) || defined (STM32L4A6xx) || \ |
|
defined (STM32L4P5xx) || defined (STM32L4Q5xx) || \ |
|
defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) |
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if((pOBInit->WRPArea == OB_WRPAREA_BANK1_AREAA) || (pOBInit->WRPArea == OB_WRPAREA_BANK1_AREAB) || |
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(pOBInit->WRPArea == OB_WRPAREA_BANK2_AREAA) || (pOBInit->WRPArea == OB_WRPAREA_BANK2_AREAB)) |
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#else |
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if((pOBInit->WRPArea == OB_WRPAREA_BANK1_AREAA) || (pOBInit->WRPArea == OB_WRPAREA_BANK1_AREAB)) |
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#endif |
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{ |
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pOBInit->OptionType |= OPTIONBYTE_WRP; |
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/* Get write protection on the selected area */ |
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FLASH_OB_GetWRP(pOBInit->WRPArea, &(pOBInit->WRPStartOffset), &(pOBInit->WRPEndOffset)); |
|
} |
|
|
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/* Get Read protection level */ |
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pOBInit->RDPLevel = FLASH_OB_GetRDP(); |
|
|
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/* Get the user option bytes */ |
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pOBInit->USERConfig = FLASH_OB_GetUser(); |
|
|
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#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ |
|
defined (STM32L496xx) || defined (STM32L4A6xx) || \ |
|
defined (STM32L4P5xx) || defined (STM32L4Q5xx) || \ |
|
defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) |
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if((pOBInit->PCROPConfig == FLASH_BANK_1) || (pOBInit->PCROPConfig == FLASH_BANK_2)) |
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#else |
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if(pOBInit->PCROPConfig == FLASH_BANK_1) |
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#endif |
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{ |
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pOBInit->OptionType |= OPTIONBYTE_PCROP; |
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/* Get the Proprietary code readout protection */ |
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FLASH_OB_GetPCROP(&(pOBInit->PCROPConfig), &(pOBInit->PCROPStartAddr), &(pOBInit->PCROPEndAddr)); |
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} |
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} |
|
|
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/** |
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* @} |
|
*/ |
|
|
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#if defined (FLASH_CFGR_LVEN) |
|
/** @defgroup FLASHEx_Exported_Functions_Group2 Extended specific configuration functions |
|
* @brief Extended specific configuration functions |
|
* |
|
@verbatim |
|
=============================================================================== |
|
##### Extended specific configuration functions ##### |
|
=============================================================================== |
|
[..] |
|
This subsection provides a set of functions allowing to manage the Extended FLASH |
|
specific configurations. |
|
|
|
@endverbatim |
|
* @{ |
|
*/ |
|
|
|
/** |
|
* @brief Configuration of the LVE pin of the Flash (managed by power controller |
|
* or forced to low in order to use an external SMPS) |
|
* @param ConfigLVE Configuration of the LVE pin, |
|
* This parameter can be one of the following values: |
|
* @arg FLASH_LVE_PIN_CTRL: LVE FLASH pin controlled by power controller |
|
* @arg FLASH_LVE_PIN_FORCED: LVE FLASH pin enforced to low (external SMPS used) |
|
* |
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* @note Before enforcing the LVE pin to low, the SOC should be in low voltage |
|
* range 2 and the voltage VDD12 should be higher than 1.08V and SMPS is ON. |
|
* |
|
* @retval HAL Status |
|
*/ |
|
HAL_StatusTypeDef HAL_FLASHEx_ConfigLVEPin(uint32_t ConfigLVE) |
|
{ |
|
HAL_StatusTypeDef status; |
|
|
|
/* Process Locked */ |
|
__HAL_LOCK(&pFlash); |
|
|
|
/* Check the parameters */ |
|
assert_param(IS_FLASH_LVE_PIN(ConfigLVE)); |
|
|
|
/* Wait for last operation to be completed */ |
|
status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); |
|
|
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if (status == HAL_OK) |
|
{ |
|
/* Check that the voltage scaling is range 2 */ |
|
if (HAL_PWREx_GetVoltageRange() == PWR_REGULATOR_VOLTAGE_SCALE2) |
|
{ |
|
/* Configure the LVEN bit */ |
|
MODIFY_REG(FLASH->CFGR, FLASH_CFGR_LVEN, ConfigLVE); |
|
|
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/* Check that the bit has been correctly configured */ |
|
if (READ_BIT(FLASH->CFGR, FLASH_CFGR_LVEN) != ConfigLVE) |
|
{ |
|
status = HAL_ERROR; |
|
} |
|
} |
|
else |
|
{ |
|
/* Not allow to force Flash LVE pin if not in voltage range 2 */ |
|
status = HAL_ERROR; |
|
} |
|
} |
|
|
|
/* Process Unlocked */ |
|
__HAL_UNLOCK(&pFlash); |
|
|
|
return status; |
|
} |
|
|
|
/** |
|
* @} |
|
*/ |
|
#endif /* FLASH_CFGR_LVEN */ |
|
|
|
/** |
|
* @} |
|
*/ |
|
|
|
/* Private functions ---------------------------------------------------------*/ |
|
|
|
/** @addtogroup FLASHEx_Private_Functions |
|
* @{ |
|
*/ |
|
/** |
|
* @brief Mass erase of FLASH memory. |
|
* @param Banks Banks to be erased |
|
* This parameter can be one of the following values: |
|
* @arg FLASH_BANK_1: Bank1 to be erased |
|
* @arg FLASH_BANK_2: Bank2 to be erased |
|
* @arg FLASH_BANK_BOTH: Bank1 and Bank2 to be erased |
|
* @retval None |
|
*/ |
|
static void FLASH_MassErase(uint32_t Banks) |
|
{ |
|
#if defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) |
|
if (READ_BIT(FLASH->OPTR, FLASH_OPTR_DBANK) != 0U) |
|
#endif |
|
{ |
|
/* Check the parameters */ |
|
assert_param(IS_FLASH_BANK(Banks)); |
|
|
|
/* Set the Mass Erase Bit for the bank 1 if requested */ |
|
if((Banks & FLASH_BANK_1) != 0U) |
|
{ |
|
SET_BIT(FLASH->CR, FLASH_CR_MER1); |
|
} |
|
|
|
#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ |
|
defined (STM32L496xx) || defined (STM32L4A6xx) || \ |
|
defined (STM32L4P5xx) || defined (STM32L4Q5xx) || \ |
|
defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) |
|
/* Set the Mass Erase Bit for the bank 2 if requested */ |
|
if((Banks & FLASH_BANK_2) != 0U) |
|
{ |
|
SET_BIT(FLASH->CR, FLASH_CR_MER2); |
|
} |
|
#endif |
|
} |
|
#if defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) |
|
else |
|
{ |
|
SET_BIT(FLASH->CR, (FLASH_CR_MER1 | FLASH_CR_MER2)); |
|
} |
|
#endif |
|
|
|
/* Proceed to erase all sectors */ |
|
SET_BIT(FLASH->CR, FLASH_CR_STRT); |
|
} |
|
|
|
/** |
|
* @brief Erase the specified FLASH memory page. |
|
* @param Page FLASH page to erase |
|
* This parameter must be a value between 0 and (max number of pages in the bank - 1) |
|
* @param Banks Bank(s) where the page will be erased |
|
* This parameter can be one of the following values: |
|
* @arg FLASH_BANK_1: Page in bank 1 to be erased |
|
* @arg FLASH_BANK_2: Page in bank 2 to be erased |
|
* @retval None |
|
*/ |
|
void FLASH_PageErase(uint32_t Page, uint32_t Banks) |
|
{ |
|
/* Check the parameters */ |
|
assert_param(IS_FLASH_PAGE(Page)); |
|
|
|
#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ |
|
defined (STM32L496xx) || defined (STM32L4A6xx) || \ |
|
defined (STM32L4P5xx) || defined (STM32L4Q5xx) || \ |
|
defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) |
|
#if defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) |
|
if(READ_BIT(FLASH->OPTR, FLASH_OPTR_DBANK) == 0U) |
|
{ |
|
CLEAR_BIT(FLASH->CR, FLASH_CR_BKER); |
|
} |
|
else |
|
#endif |
|
{ |
|
assert_param(IS_FLASH_BANK_EXCLUSIVE(Banks)); |
|
|
|
if((Banks & FLASH_BANK_1) != 0U) |
|
{ |
|
CLEAR_BIT(FLASH->CR, FLASH_CR_BKER); |
|
} |
|
else |
|
{ |
|
SET_BIT(FLASH->CR, FLASH_CR_BKER); |
|
} |
|
} |
|
#else |
|
/* Prevent unused argument(s) compilation warning */ |
|
UNUSED(Banks); |
|
#endif |
|
|
|
/* Proceed to erase the page */ |
|
MODIFY_REG(FLASH->CR, FLASH_CR_PNB, ((Page & 0xFFU) << FLASH_CR_PNB_Pos)); |
|
SET_BIT(FLASH->CR, FLASH_CR_PER); |
|
SET_BIT(FLASH->CR, FLASH_CR_STRT); |
|
} |
|
|
|
/** |
|
* @brief Flush the instruction and data caches. |
|
* @retval None |
|
*/ |
|
void FLASH_FlushCaches(void) |
|
{ |
|
FLASH_CacheTypeDef cache = pFlash.CacheToReactivate; |
|
|
|
/* Flush instruction cache */ |
|
if((cache == FLASH_CACHE_ICACHE_ENABLED) || |
|
(cache == FLASH_CACHE_ICACHE_DCACHE_ENABLED)) |
|
{ |
|
/* Disable instruction cache */ |
|
__HAL_FLASH_INSTRUCTION_CACHE_DISABLE(); |
|
/* Reset instruction cache */ |
|
__HAL_FLASH_INSTRUCTION_CACHE_RESET(); |
|
/* Enable instruction cache */ |
|
__HAL_FLASH_INSTRUCTION_CACHE_ENABLE(); |
|
} |
|
|
|
/* Flush data cache */ |
|
if((cache == FLASH_CACHE_DCACHE_ENABLED) || |
|
(cache == FLASH_CACHE_ICACHE_DCACHE_ENABLED)) |
|
{ |
|
/* Reset data cache */ |
|
__HAL_FLASH_DATA_CACHE_RESET(); |
|
/* Enable data cache */ |
|
__HAL_FLASH_DATA_CACHE_ENABLE(); |
|
} |
|
|
|
/* Reset internal variable */ |
|
pFlash.CacheToReactivate = FLASH_CACHE_DISABLED; |
|
} |
|
|
|
/** |
|
* @brief Configure the write protection of the desired pages. |
|
* |
|
* @note When the memory read protection level is selected (RDP level = 1), |
|
* it is not possible to program or erase Flash memory if the CPU debug |
|
* features are connected (JTAG or single wire) or boot code is being |
|
* executed from RAM or System flash, even if WRP is not activated. |
|
* @note To configure the WRP options, the option lock bit OPTLOCK must be |
|
* cleared with the call of the HAL_FLASH_OB_Unlock() function. |
|
* @note To validate the WRP options, the option bytes must be reloaded |
|
* through the call of the HAL_FLASH_OB_Launch() function. |
|
* |
|
* @param WRPArea specifies the area to be configured. |
|
* This parameter can be one of the following values: |
|
* @arg OB_WRPAREA_BANK1_AREAA: Flash Bank 1 Area A |
|
* @arg OB_WRPAREA_BANK1_AREAB: Flash Bank 1 Area B |
|
* @arg OB_WRPAREA_BANK2_AREAA: Flash Bank 2 Area A (don't apply for STM32L43x/STM32L44x devices) |
|
* @arg OB_WRPAREA_BANK2_AREAB: Flash Bank 2 Area B (don't apply for STM32L43x/STM32L44x devices) |
|
* |
|
* @param WRPStartOffset specifies the start page of the write protected area |
|
* This parameter can be page number between 0 and (max number of pages in the bank - 1) |
|
* |
|
* @param WRDPEndOffset specifies the end page of the write protected area |
|
* This parameter can be page number between WRPStartOffset and (max number of pages in the bank - 1) |
|
* |
|
* @retval HAL Status |
|
*/ |
|
static HAL_StatusTypeDef FLASH_OB_WRPConfig(uint32_t WRPArea, uint32_t WRPStartOffset, uint32_t WRDPEndOffset) |
|
{ |
|
HAL_StatusTypeDef status; |
|
|
|
/* Check the parameters */ |
|
assert_param(IS_OB_WRPAREA(WRPArea)); |
|
assert_param(IS_FLASH_PAGE(WRPStartOffset)); |
|
assert_param(IS_FLASH_PAGE(WRDPEndOffset)); |
|
|
|
/* Wait for last operation to be completed */ |
|
status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); |
|
|
|
if(status == HAL_OK) |
|
{ |
|
/* Configure the write protected area */ |
|
if(WRPArea == OB_WRPAREA_BANK1_AREAA) |
|
{ |
|
MODIFY_REG(FLASH->WRP1AR, (FLASH_WRP1AR_WRP1A_STRT | FLASH_WRP1AR_WRP1A_END), |
|
(WRPStartOffset | (WRDPEndOffset << 16))); |
|
} |
|
else if(WRPArea == OB_WRPAREA_BANK1_AREAB) |
|
{ |
|
MODIFY_REG(FLASH->WRP1BR, (FLASH_WRP1BR_WRP1B_STRT | FLASH_WRP1BR_WRP1B_END), |
|
(WRPStartOffset | (WRDPEndOffset << 16))); |
|
} |
|
#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ |
|
defined (STM32L496xx) || defined (STM32L4A6xx) || \ |
|
defined (STM32L4P5xx) || defined (STM32L4Q5xx) || \ |
|
defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) |
|
else if(WRPArea == OB_WRPAREA_BANK2_AREAA) |
|
{ |
|
MODIFY_REG(FLASH->WRP2AR, (FLASH_WRP2AR_WRP2A_STRT | FLASH_WRP2AR_WRP2A_END), |
|
(WRPStartOffset | (WRDPEndOffset << 16))); |
|
} |
|
else if(WRPArea == OB_WRPAREA_BANK2_AREAB) |
|
{ |
|
MODIFY_REG(FLASH->WRP2BR, (FLASH_WRP2BR_WRP2B_STRT | FLASH_WRP2BR_WRP2B_END), |
|
(WRPStartOffset | (WRDPEndOffset << 16))); |
|
} |
|
#endif |
|
else |
|
{ |
|
/* Nothing to do */ |
|
} |
|
|
|
/* Set OPTSTRT Bit */ |
|
SET_BIT(FLASH->CR, FLASH_CR_OPTSTRT); |
|
|
|
/* Wait for last operation to be completed */ |
|
status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); |
|
|
|
/* If the option byte program operation is completed, disable the OPTSTRT Bit */ |
|
CLEAR_BIT(FLASH->CR, FLASH_CR_OPTSTRT); |
|
} |
|
|
|
return status; |
|
} |
|
|
|
/** |
|
* @brief Set the read protection level. |
|
* |
|
* @note To configure the RDP level, the option lock bit OPTLOCK must be |
|
* cleared with the call of the HAL_FLASH_OB_Unlock() function. |
|
* @note To validate the RDP level, the option bytes must be reloaded |
|
* through the call of the HAL_FLASH_OB_Launch() function. |
|
* @note !!! Warning : When enabling OB_RDP level 2 it's no more possible |
|
* to go back to level 1 or 0 !!! |
|
* |
|
* @param RDPLevel specifies the read protection level. |
|
* This parameter can be one of the following values: |
|
* @arg OB_RDP_LEVEL_0: No protection |
|
* @arg OB_RDP_LEVEL_1: Read protection of the memory |
|
* @arg OB_RDP_LEVEL_2: Full chip protection |
|
* |
|
* @retval HAL status |
|
*/ |
|
static HAL_StatusTypeDef FLASH_OB_RDPConfig(uint32_t RDPLevel) |
|
{ |
|
HAL_StatusTypeDef status; |
|
|
|
/* Check the parameters */ |
|
assert_param(IS_OB_RDP_LEVEL(RDPLevel)); |
|
|
|
/* Wait for last operation to be completed */ |
|
status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); |
|
|
|
if(status == HAL_OK) |
|
{ |
|
/* Configure the RDP level in the option bytes register */ |
|
MODIFY_REG(FLASH->OPTR, FLASH_OPTR_RDP, RDPLevel); |
|
|
|
/* Set OPTSTRT Bit */ |
|
SET_BIT(FLASH->CR, FLASH_CR_OPTSTRT); |
|
|
|
/* Wait for last operation to be completed */ |
|
status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); |
|
|
|
/* If the option byte program operation is completed, disable the OPTSTRT Bit */ |
|
CLEAR_BIT(FLASH->CR, FLASH_CR_OPTSTRT); |
|
} |
|
|
|
return status; |
|
} |
|
|
|
/** |
|
* @brief Program the FLASH User Option Byte. |
|
* |
|
* @note To configure the user option bytes, the option lock bit OPTLOCK must |
|
* be cleared with the call of the HAL_FLASH_OB_Unlock() function. |
|
* @note To validate the user option bytes, the option bytes must be reloaded |
|
* through the call of the HAL_FLASH_OB_Launch() function. |
|
* |
|
* @param UserType The FLASH User Option Bytes to be modified |
|
* @param UserConfig The FLASH User Option Bytes values: |
|
* BOR_LEV(Bit8-10), nRST_STOP(Bit12), nRST_STDBY(Bit13), IWDG_SW(Bit16), |
|
* IWDG_STOP(Bit17), IWDG_STDBY(Bit18), WWDG_SW(Bit19), BFB2(Bit20), |
|
* DUALBANK(Bit21), nBOOT1(Bit23), SRAM2_PE(Bit24) and SRAM2_RST(Bit25). |
|
* |
|
* @retval HAL status |
|
*/ |
|
static HAL_StatusTypeDef FLASH_OB_UserConfig(uint32_t UserType, uint32_t UserConfig) |
|
{ |
|
uint32_t optr_reg_val = 0; |
|
uint32_t optr_reg_mask = 0; |
|
HAL_StatusTypeDef status; |
|
|
|
/* Check the parameters */ |
|
assert_param(IS_OB_USER_TYPE(UserType)); |
|
|
|
/* Wait for last operation to be completed */ |
|
status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); |
|
|
|
if(status == HAL_OK) |
|
{ |
|
if((UserType & OB_USER_BOR_LEV) != 0U) |
|
{ |
|
/* BOR level option byte should be modified */ |
|
assert_param(IS_OB_USER_BOR_LEVEL(UserConfig & FLASH_OPTR_BOR_LEV)); |
|
|
|
/* Set value and mask for BOR level option byte */ |
|
optr_reg_val |= (UserConfig & FLASH_OPTR_BOR_LEV); |
|
optr_reg_mask |= FLASH_OPTR_BOR_LEV; |
|
} |
|
|
|
if((UserType & OB_USER_nRST_STOP) != 0U) |
|
{ |
|
/* nRST_STOP option byte should be modified */ |
|
assert_param(IS_OB_USER_STOP(UserConfig & FLASH_OPTR_nRST_STOP)); |
|
|
|
/* Set value and mask for nRST_STOP option byte */ |
|
optr_reg_val |= (UserConfig & FLASH_OPTR_nRST_STOP); |
|
optr_reg_mask |= FLASH_OPTR_nRST_STOP; |
|
} |
|
|
|
if((UserType & OB_USER_nRST_STDBY) != 0U) |
|
{ |
|
/* nRST_STDBY option byte should be modified */ |
|
assert_param(IS_OB_USER_STANDBY(UserConfig & FLASH_OPTR_nRST_STDBY)); |
|
|
|
/* Set value and mask for nRST_STDBY option byte */ |
|
optr_reg_val |= (UserConfig & FLASH_OPTR_nRST_STDBY); |
|
optr_reg_mask |= FLASH_OPTR_nRST_STDBY; |
|
} |
|
|
|
if((UserType & OB_USER_nRST_SHDW) != 0U) |
|
{ |
|
/* nRST_SHDW option byte should be modified */ |
|
assert_param(IS_OB_USER_SHUTDOWN(UserConfig & FLASH_OPTR_nRST_SHDW)); |
|
|
|
/* Set value and mask for nRST_SHDW option byte */ |
|
optr_reg_val |= (UserConfig & FLASH_OPTR_nRST_SHDW); |
|
optr_reg_mask |= FLASH_OPTR_nRST_SHDW; |
|
} |
|
|
|
if((UserType & OB_USER_IWDG_SW) != 0U) |
|
{ |
|
/* IWDG_SW option byte should be modified */ |
|
assert_param(IS_OB_USER_IWDG(UserConfig & FLASH_OPTR_IWDG_SW)); |
|
|
|
/* Set value and mask for IWDG_SW option byte */ |
|
optr_reg_val |= (UserConfig & FLASH_OPTR_IWDG_SW); |
|
optr_reg_mask |= FLASH_OPTR_IWDG_SW; |
|
} |
|
|
|
if((UserType & OB_USER_IWDG_STOP) != 0U) |
|
{ |
|
/* IWDG_STOP option byte should be modified */ |
|
assert_param(IS_OB_USER_IWDG_STOP(UserConfig & FLASH_OPTR_IWDG_STOP)); |
|
|
|
/* Set value and mask for IWDG_STOP option byte */ |
|
optr_reg_val |= (UserConfig & FLASH_OPTR_IWDG_STOP); |
|
optr_reg_mask |= FLASH_OPTR_IWDG_STOP; |
|
} |
|
|
|
if((UserType & OB_USER_IWDG_STDBY) != 0U) |
|
{ |
|
/* IWDG_STDBY option byte should be modified */ |
|
assert_param(IS_OB_USER_IWDG_STDBY(UserConfig & FLASH_OPTR_IWDG_STDBY)); |
|
|
|
/* Set value and mask for IWDG_STDBY option byte */ |
|
optr_reg_val |= (UserConfig & FLASH_OPTR_IWDG_STDBY); |
|
optr_reg_mask |= FLASH_OPTR_IWDG_STDBY; |
|
} |
|
|
|
if((UserType & OB_USER_WWDG_SW) != 0U) |
|
{ |
|
/* WWDG_SW option byte should be modified */ |
|
assert_param(IS_OB_USER_WWDG(UserConfig & FLASH_OPTR_WWDG_SW)); |
|
|
|
/* Set value and mask for WWDG_SW option byte */ |
|
optr_reg_val |= (UserConfig & FLASH_OPTR_WWDG_SW); |
|
optr_reg_mask |= FLASH_OPTR_WWDG_SW; |
|
} |
|
|
|
#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ |
|
defined (STM32L496xx) || defined (STM32L4A6xx) || \ |
|
defined (STM32L4P5xx) || defined (STM32L4Q5xx) || \ |
|
defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) |
|
if((UserType & OB_USER_BFB2) != 0U) |
|
{ |
|
/* BFB2 option byte should be modified */ |
|
assert_param(IS_OB_USER_BFB2(UserConfig & FLASH_OPTR_BFB2)); |
|
|
|
/* Set value and mask for BFB2 option byte */ |
|
optr_reg_val |= (UserConfig & FLASH_OPTR_BFB2); |
|
optr_reg_mask |= FLASH_OPTR_BFB2; |
|
} |
|
|
|
if((UserType & OB_USER_DUALBANK) != 0U) |
|
{ |
|
#if defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) |
|
/* DUALBANK option byte should be modified */ |
|
assert_param(IS_OB_USER_DUALBANK(UserConfig & FLASH_OPTR_DB1M)); |
|
|
|
/* Set value and mask for DUALBANK option byte */ |
|
optr_reg_val |= (UserConfig & FLASH_OPTR_DB1M); |
|
optr_reg_mask |= FLASH_OPTR_DB1M; |
|
#else |
|
/* DUALBANK option byte should be modified */ |
|
assert_param(IS_OB_USER_DUALBANK(UserConfig & FLASH_OPTR_DUALBANK)); |
|
|
|
/* Set value and mask for DUALBANK option byte */ |
|
optr_reg_val |= (UserConfig & FLASH_OPTR_DUALBANK); |
|
optr_reg_mask |= FLASH_OPTR_DUALBANK; |
|
#endif |
|
} |
|
#endif |
|
|
|
if((UserType & OB_USER_nBOOT1) != 0U) |
|
{ |
|
/* nBOOT1 option byte should be modified */ |
|
assert_param(IS_OB_USER_BOOT1(UserConfig & FLASH_OPTR_nBOOT1)); |
|
|
|
/* Set value and mask for nBOOT1 option byte */ |
|
optr_reg_val |= (UserConfig & FLASH_OPTR_nBOOT1); |
|
optr_reg_mask |= FLASH_OPTR_nBOOT1; |
|
} |
|
|
|
if((UserType & OB_USER_SRAM2_PE) != 0U) |
|
{ |
|
/* SRAM2_PE option byte should be modified */ |
|
assert_param(IS_OB_USER_SRAM2_PARITY(UserConfig & FLASH_OPTR_SRAM2_PE)); |
|
|
|
/* Set value and mask for SRAM2_PE option byte */ |
|
optr_reg_val |= (UserConfig & FLASH_OPTR_SRAM2_PE); |
|
optr_reg_mask |= FLASH_OPTR_SRAM2_PE; |
|
} |
|
|
|
if((UserType & OB_USER_SRAM2_RST) != 0U) |
|
{ |
|
/* SRAM2_RST option byte should be modified */ |
|
assert_param(IS_OB_USER_SRAM2_RST(UserConfig & FLASH_OPTR_SRAM2_RST)); |
|
|
|
/* Set value and mask for SRAM2_RST option byte */ |
|
optr_reg_val |= (UserConfig & FLASH_OPTR_SRAM2_RST); |
|
optr_reg_mask |= FLASH_OPTR_SRAM2_RST; |
|
} |
|
|
|
#if defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || \ |
|
defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || \ |
|
defined (STM32L496xx) || defined (STM32L4A6xx) || \ |
|
defined (STM32L4P5xx) || defined (STM32L4Q5xx) || \ |
|
defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) |
|
if((UserType & OB_USER_nSWBOOT0) != 0U) |
|
{ |
|
/* nSWBOOT0 option byte should be modified */ |
|
assert_param(IS_OB_USER_SWBOOT0(UserConfig & FLASH_OPTR_nSWBOOT0)); |
|
|
|
/* Set value and mask for nSWBOOT0 option byte */ |
|
optr_reg_val |= (UserConfig & FLASH_OPTR_nSWBOOT0); |
|
optr_reg_mask |= FLASH_OPTR_nSWBOOT0; |
|
} |
|
|
|
if((UserType & OB_USER_nBOOT0) != 0U) |
|
{ |
|
/* nBOOT0 option byte should be modified */ |
|
assert_param(IS_OB_USER_BOOT0(UserConfig & FLASH_OPTR_nBOOT0)); |
|
|
|
/* Set value and mask for nBOOT0 option byte */ |
|
optr_reg_val |= (UserConfig & FLASH_OPTR_nBOOT0); |
|
optr_reg_mask |= FLASH_OPTR_nBOOT0; |
|
} |
|
#endif |
|
|
|
/* Configure the option bytes register */ |
|
MODIFY_REG(FLASH->OPTR, optr_reg_mask, optr_reg_val); |
|
|
|
/* Set OPTSTRT Bit */ |
|
SET_BIT(FLASH->CR, FLASH_CR_OPTSTRT); |
|
|
|
/* Wait for last operation to be completed */ |
|
status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); |
|
|
|
/* If the option byte program operation is completed, disable the OPTSTRT Bit */ |
|
CLEAR_BIT(FLASH->CR, FLASH_CR_OPTSTRT); |
|
} |
|
|
|
return status; |
|
} |
|
|
|
/** |
|
* @brief Configure the Proprietary code readout protection of the desired addresses. |
|
* |
|
* @note To configure the PCROP options, the option lock bit OPTLOCK must be |
|
* cleared with the call of the HAL_FLASH_OB_Unlock() function. |
|
* @note To validate the PCROP options, the option bytes must be reloaded |
|
* through the call of the HAL_FLASH_OB_Launch() function. |
|
* |
|
* @param PCROPConfig specifies the configuration (Bank to be configured and PCROP_RDP option). |
|
* This parameter must be a combination of FLASH_BANK_1 or FLASH_BANK_2 |
|
* with OB_PCROP_RDP_NOT_ERASE or OB_PCROP_RDP_ERASE |
|
* |
|
* @param PCROPStartAddr specifies the start address of the Proprietary code readout protection |
|
* This parameter can be an address between begin and end of the bank |
|
* |
|
* @param PCROPEndAddr specifies the end address of the Proprietary code readout protection |
|
* This parameter can be an address between PCROPStartAddr and end of the bank |
|
* |
|
* @retval HAL Status |
|
*/ |
|
static HAL_StatusTypeDef FLASH_OB_PCROPConfig(uint32_t PCROPConfig, uint32_t PCROPStartAddr, uint32_t PCROPEndAddr) |
|
{ |
|
HAL_StatusTypeDef status; |
|
uint32_t reg_value; |
|
uint32_t bank1_addr; |
|
#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ |
|
defined (STM32L496xx) || defined (STM32L4A6xx) || \ |
|
defined (STM32L4P5xx) || defined (STM32L4Q5xx) || \ |
|
defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) |
|
uint32_t bank2_addr; |
|
#endif |
|
|
|
/* Check the parameters */ |
|
assert_param(IS_FLASH_BANK_EXCLUSIVE(PCROPConfig & FLASH_BANK_BOTH)); |
|
assert_param(IS_OB_PCROP_RDP(PCROPConfig & FLASH_PCROP1ER_PCROP_RDP)); |
|
assert_param(IS_FLASH_MAIN_MEM_ADDRESS(PCROPStartAddr)); |
|
assert_param(IS_FLASH_MAIN_MEM_ADDRESS(PCROPEndAddr)); |
|
|
|
/* Wait for last operation to be completed */ |
|
status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); |
|
|
|
if(status == HAL_OK) |
|
{ |
|
#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ |
|
defined (STM32L496xx) || defined (STM32L4A6xx) || \ |
|
defined (STM32L4P5xx) || defined (STM32L4Q5xx) || \ |
|
defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) |
|
/* Get the information about the bank swapping */ |
|
if (READ_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_FB_MODE) == 0U) |
|
{ |
|
bank1_addr = FLASH_BASE; |
|
bank2_addr = FLASH_BASE + FLASH_BANK_SIZE; |
|
} |
|
else |
|
{ |
|
bank1_addr = FLASH_BASE + FLASH_BANK_SIZE; |
|
bank2_addr = FLASH_BASE; |
|
} |
|
#else |
|
bank1_addr = FLASH_BASE; |
|
#endif |
|
|
|
#if defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) |
|
if (READ_BIT(FLASH->OPTR, FLASH_OPTR_DBANK) == 0U) |
|
{ |
|
/* Configure the Proprietary code readout protection */ |
|
if((PCROPConfig & FLASH_BANK_BOTH) == FLASH_BANK_1) |
|
{ |
|
reg_value = ((PCROPStartAddr - FLASH_BASE) >> 4); |
|
MODIFY_REG(FLASH->PCROP1SR, FLASH_PCROP1SR_PCROP1_STRT, reg_value); |
|
|
|
reg_value = ((PCROPEndAddr - FLASH_BASE) >> 4); |
|
MODIFY_REG(FLASH->PCROP1ER, FLASH_PCROP1ER_PCROP1_END, reg_value); |
|
} |
|
else if((PCROPConfig & FLASH_BANK_BOTH) == FLASH_BANK_2) |
|
{ |
|
reg_value = ((PCROPStartAddr - FLASH_BASE) >> 4); |
|
MODIFY_REG(FLASH->PCROP2SR, FLASH_PCROP2SR_PCROP2_STRT, reg_value); |
|
|
|
reg_value = ((PCROPEndAddr - FLASH_BASE) >> 4); |
|
MODIFY_REG(FLASH->PCROP2ER, FLASH_PCROP2ER_PCROP2_END, reg_value); |
|
} |
|
else |
|
{ |
|
/* Nothing to do */ |
|
} |
|
} |
|
else |
|
#endif |
|
{ |
|
/* Configure the Proprietary code readout protection */ |
|
if((PCROPConfig & FLASH_BANK_BOTH) == FLASH_BANK_1) |
|
{ |
|
reg_value = ((PCROPStartAddr - bank1_addr) >> 3); |
|
MODIFY_REG(FLASH->PCROP1SR, FLASH_PCROP1SR_PCROP1_STRT, reg_value); |
|
|
|
reg_value = ((PCROPEndAddr - bank1_addr) >> 3); |
|
MODIFY_REG(FLASH->PCROP1ER, FLASH_PCROP1ER_PCROP1_END, reg_value); |
|
} |
|
#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ |
|
defined (STM32L496xx) || defined (STM32L4A6xx) || \ |
|
defined (STM32L4P5xx) || defined (STM32L4Q5xx) || \ |
|
defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) |
|
else if((PCROPConfig & FLASH_BANK_BOTH) == FLASH_BANK_2) |
|
{ |
|
reg_value = ((PCROPStartAddr - bank2_addr) >> 3); |
|
MODIFY_REG(FLASH->PCROP2SR, FLASH_PCROP2SR_PCROP2_STRT, reg_value); |
|
|
|
reg_value = ((PCROPEndAddr - bank2_addr) >> 3); |
|
MODIFY_REG(FLASH->PCROP2ER, FLASH_PCROP2ER_PCROP2_END, reg_value); |
|
} |
|
#endif |
|
else |
|
{ |
|
/* Nothing to do */ |
|
} |
|
} |
|
|
|
MODIFY_REG(FLASH->PCROP1ER, FLASH_PCROP1ER_PCROP_RDP, (PCROPConfig & FLASH_PCROP1ER_PCROP_RDP)); |
|
|
|
/* Set OPTSTRT Bit */ |
|
SET_BIT(FLASH->CR, FLASH_CR_OPTSTRT); |
|
|
|
/* Wait for last operation to be completed */ |
|
status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); |
|
|
|
/* If the option byte program operation is completed, disable the OPTSTRT Bit */ |
|
CLEAR_BIT(FLASH->CR, FLASH_CR_OPTSTRT); |
|
} |
|
|
|
return status; |
|
} |
|
|
|
/** |
|
* @brief Return the FLASH Write Protection Option Bytes value. |
|
* |
|
* @param[in] WRPArea: specifies the area to be returned. |
|
* This parameter can be one of the following values: |
|
* @arg OB_WRPAREA_BANK1_AREAA: Flash Bank 1 Area A |
|
* @arg OB_WRPAREA_BANK1_AREAB: Flash Bank 1 Area B |
|
* @arg OB_WRPAREA_BANK2_AREAA: Flash Bank 2 Area A (don't apply to STM32L43x/STM32L44x devices) |
|
* @arg OB_WRPAREA_BANK2_AREAB: Flash Bank 2 Area B (don't apply to STM32L43x/STM32L44x devices) |
|
* |
|
* @param[out] WRPStartOffset: specifies the address where to copied the start page |
|
* of the write protected area |
|
* |
|
* @param[out] WRDPEndOffset: specifies the address where to copied the end page of |
|
* the write protected area |
|
* |
|
* @retval None |
|
*/ |
|
static void FLASH_OB_GetWRP(uint32_t WRPArea, uint32_t * WRPStartOffset, uint32_t * WRDPEndOffset) |
|
{ |
|
/* Get the configuration of the write protected area */ |
|
if(WRPArea == OB_WRPAREA_BANK1_AREAA) |
|
{ |
|
*WRPStartOffset = READ_BIT(FLASH->WRP1AR, FLASH_WRP1AR_WRP1A_STRT); |
|
*WRDPEndOffset = (READ_BIT(FLASH->WRP1AR, FLASH_WRP1AR_WRP1A_END) >> 16); |
|
} |
|
else if(WRPArea == OB_WRPAREA_BANK1_AREAB) |
|
{ |
|
*WRPStartOffset = READ_BIT(FLASH->WRP1BR, FLASH_WRP1BR_WRP1B_STRT); |
|
*WRDPEndOffset = (READ_BIT(FLASH->WRP1BR, FLASH_WRP1BR_WRP1B_END) >> 16); |
|
} |
|
#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ |
|
defined (STM32L496xx) || defined (STM32L4A6xx) || \ |
|
defined (STM32L4P5xx) || defined (STM32L4Q5xx) || \ |
|
defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) |
|
else if(WRPArea == OB_WRPAREA_BANK2_AREAA) |
|
{ |
|
*WRPStartOffset = READ_BIT(FLASH->WRP2AR, FLASH_WRP2AR_WRP2A_STRT); |
|
*WRDPEndOffset = (READ_BIT(FLASH->WRP2AR, FLASH_WRP2AR_WRP2A_END) >> 16); |
|
} |
|
else if(WRPArea == OB_WRPAREA_BANK2_AREAB) |
|
{ |
|
*WRPStartOffset = READ_BIT(FLASH->WRP2BR, FLASH_WRP2BR_WRP2B_STRT); |
|
*WRDPEndOffset = (READ_BIT(FLASH->WRP2BR, FLASH_WRP2BR_WRP2B_END) >> 16); |
|
} |
|
#endif |
|
else |
|
{ |
|
/* Nothing to do */ |
|
} |
|
} |
|
|
|
/** |
|
* @brief Return the FLASH Read Protection level. |
|
* @retval FLASH ReadOut Protection Status: |
|
* This return value can be one of the following values: |
|
* @arg OB_RDP_LEVEL_0: No protection |
|
* @arg OB_RDP_LEVEL_1: Read protection of the memory |
|
* @arg OB_RDP_LEVEL_2: Full chip protection |
|
*/ |
|
static uint32_t FLASH_OB_GetRDP(void) |
|
{ |
|
uint32_t rdp_level = READ_BIT(FLASH->OPTR, FLASH_OPTR_RDP); |
|
|
|
if ((rdp_level != OB_RDP_LEVEL_0) && (rdp_level != OB_RDP_LEVEL_2)) |
|
{ |
|
return (OB_RDP_LEVEL_1); |
|
} |
|
else |
|
{ |
|
return (READ_BIT(FLASH->OPTR, FLASH_OPTR_RDP)); |
|
} |
|
} |
|
|
|
/** |
|
* @brief Return the FLASH User Option Byte value. |
|
* @retval The FLASH User Option Bytes values: |
|
* For STM32L47x/STM32L48x devices : |
|
* BOR_LEV(Bit8-10), nRST_STOP(Bit12), nRST_STDBY(Bit13), nRST_SHDW(Bit14), |
|
* IWDG_SW(Bit16), IWDG_STOP(Bit17), IWDG_STDBY(Bit18), WWDG_SW(Bit19), |
|
* BFB2(Bit20), DUALBANK(Bit21), nBOOT1(Bit23), SRAM2_PE(Bit24) and SRAM2_RST(Bit25). |
|
* For STM32L43x/STM32L44x devices : |
|
* BOR_LEV(Bit8-10), nRST_STOP(Bit12), nRST_STDBY(Bit13), nRST_SHDW(Bit14), |
|
* IWDG_SW(Bit16), IWDG_STOP(Bit17), IWDG_STDBY(Bit18), WWDG_SW(Bit19), |
|
* nBOOT1(Bit23), SRAM2_PE(Bit24), SRAM2_RST(Bit25), nSWBOOT0(Bit26) and nBOOT0(Bit27). |
|
*/ |
|
static uint32_t FLASH_OB_GetUser(void) |
|
{ |
|
uint32_t user_config = READ_REG(FLASH->OPTR); |
|
CLEAR_BIT(user_config, FLASH_OPTR_RDP); |
|
|
|
return user_config; |
|
} |
|
|
|
/** |
|
* @brief Return the FLASH Write Protection Option Bytes value. |
|
* |
|
* @param PCROPConfig [inout]: specifies the configuration (Bank to be configured and PCROP_RDP option). |
|
* This parameter must be a combination of FLASH_BANK_1 or FLASH_BANK_2 |
|
* with OB_PCROP_RDP_NOT_ERASE or OB_PCROP_RDP_ERASE |
|
* |
|
* @param PCROPStartAddr [out]: specifies the address where to copied the start address |
|
* of the Proprietary code readout protection |
|
* |
|
* @param PCROPEndAddr [out]: specifies the address where to copied the end address of |
|
* the Proprietary code readout protection |
|
* |
|
* @retval None |
|
*/ |
|
static void FLASH_OB_GetPCROP(uint32_t * PCROPConfig, uint32_t * PCROPStartAddr, uint32_t * PCROPEndAddr) |
|
{ |
|
uint32_t reg_value; |
|
uint32_t bank1_addr; |
|
#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ |
|
defined (STM32L496xx) || defined (STM32L4A6xx) || \ |
|
defined (STM32L4P5xx) || defined (STM32L4Q5xx) || \ |
|
defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) |
|
uint32_t bank2_addr; |
|
#endif |
|
|
|
#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ |
|
defined (STM32L496xx) || defined (STM32L4A6xx) || \ |
|
defined (STM32L4P5xx) || defined (STM32L4Q5xx) || \ |
|
defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) |
|
/* Get the information about the bank swapping */ |
|
if (READ_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_FB_MODE) == 0U) |
|
{ |
|
bank1_addr = FLASH_BASE; |
|
bank2_addr = FLASH_BASE + FLASH_BANK_SIZE; |
|
} |
|
else |
|
{ |
|
bank1_addr = FLASH_BASE + FLASH_BANK_SIZE; |
|
bank2_addr = FLASH_BASE; |
|
} |
|
#else |
|
bank1_addr = FLASH_BASE; |
|
#endif |
|
|
|
#if defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) |
|
if (READ_BIT(FLASH->OPTR, FLASH_OPTR_DBANK) == 0U) |
|
{ |
|
if(((*PCROPConfig) & FLASH_BANK_BOTH) == FLASH_BANK_1) |
|
{ |
|
reg_value = (READ_REG(FLASH->PCROP1SR) & FLASH_PCROP1SR_PCROP1_STRT); |
|
*PCROPStartAddr = (reg_value << 4) + FLASH_BASE; |
|
|
|
reg_value = (READ_REG(FLASH->PCROP1ER) & FLASH_PCROP1ER_PCROP1_END); |
|
*PCROPEndAddr = (reg_value << 4) + FLASH_BASE + 0xFU; |
|
} |
|
else if(((*PCROPConfig) & FLASH_BANK_BOTH) == FLASH_BANK_2) |
|
{ |
|
reg_value = (READ_REG(FLASH->PCROP2SR) & FLASH_PCROP2SR_PCROP2_STRT); |
|
*PCROPStartAddr = (reg_value << 4) + FLASH_BASE; |
|
|
|
reg_value = (READ_REG(FLASH->PCROP2ER) & FLASH_PCROP2ER_PCROP2_END); |
|
*PCROPEndAddr = (reg_value << 4) + FLASH_BASE + 0xFU;; |
|
} |
|
else |
|
{ |
|
/* Nothing to do */ |
|
} |
|
} |
|
else |
|
#endif |
|
{ |
|
if(((*PCROPConfig) & FLASH_BANK_BOTH) == FLASH_BANK_1) |
|
{ |
|
reg_value = (READ_REG(FLASH->PCROP1SR) & FLASH_PCROP1SR_PCROP1_STRT); |
|
*PCROPStartAddr = (reg_value << 3) + bank1_addr; |
|
|
|
reg_value = (READ_REG(FLASH->PCROP1ER) & FLASH_PCROP1ER_PCROP1_END); |
|
*PCROPEndAddr = (reg_value << 3) + bank1_addr + 0x7U; |
|
} |
|
#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ |
|
defined (STM32L496xx) || defined (STM32L4A6xx) || \ |
|
defined (STM32L4P5xx) || defined (STM32L4Q5xx) || \ |
|
defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) |
|
else if(((*PCROPConfig) & FLASH_BANK_BOTH) == FLASH_BANK_2) |
|
{ |
|
reg_value = (READ_REG(FLASH->PCROP2SR) & FLASH_PCROP2SR_PCROP2_STRT); |
|
*PCROPStartAddr = (reg_value << 3) + bank2_addr; |
|
|
|
reg_value = (READ_REG(FLASH->PCROP2ER) & FLASH_PCROP2ER_PCROP2_END); |
|
*PCROPEndAddr = (reg_value << 3) + bank2_addr + 0x7U; |
|
} |
|
#endif |
|
else |
|
{ |
|
/* Nothing to do */ |
|
} |
|
} |
|
|
|
*PCROPConfig |= (READ_REG(FLASH->PCROP1ER) & FLASH_PCROP1ER_PCROP_RDP); |
|
} |
|
/** |
|
* @} |
|
*/ |
|
|
|
/** |
|
* @} |
|
*/ |
|
|
|
#endif /* HAL_FLASH_MODULE_ENABLED */ |
|
|
|
/** |
|
* @} |
|
*/ |
|
|
|
/** |
|
* @} |
|
*/ |
|
|
|
|