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860 lines
31 KiB
860 lines
31 KiB
/** |
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****************************************************************************** |
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* @file stm32l4xx_ll_fmc.c |
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* @author MCD Application Team |
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* @brief FMC Low Layer HAL module driver. |
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* |
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* This file provides firmware functions to manage the following |
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* functionalities of the Flexible Memory Controller (FMC) peripheral memories: |
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* + Initialization/de-initialization functions |
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* + Peripheral Control functions |
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* + Peripheral State functions |
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* |
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****************************************************************************** |
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* @attention |
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* |
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* Copyright (c) 2017 STMicroelectronics. |
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* All rights reserved. |
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* |
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* This software is licensed under terms that can be found in the LICENSE file |
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* in the root directory of this software component. |
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* If no LICENSE file comes with this software, it is provided AS-IS. |
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* |
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****************************************************************************** |
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@verbatim |
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============================================================================== |
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##### FMC peripheral features ##### |
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============================================================================== |
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[..] The Flexible memory controller (FMC) includes following memory controllers: |
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(+) The NOR/PSRAM memory controller |
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(+) The NAND memory controller |
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[..] The FMC functional block makes the interface with synchronous and asynchronous static |
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memories. Its main purposes are: |
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(+) to translate AHB transactions into the appropriate external device protocol |
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(+) to meet the access time requirements of the external memory devices |
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[..] All external memories share the addresses, data and control signals with the controller. |
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Each external device is accessed by means of a unique Chip Select. The FMC performs |
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only one access at a time to an external device. |
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The main features of the FMC controller are the following: |
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(+) Interface with static-memory mapped devices including: |
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(++) Static random access memory (SRAM) |
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(++) Read-only memory (ROM) |
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(++) NOR Flash memory/OneNAND Flash memory |
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(++) PSRAM (4 memory banks) |
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(++) Two banks of NAND Flash memory with ECC hardware to check up to 8 Kbytes of |
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data |
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(+) Independent Chip Select control for each memory bank |
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(+) Independent configuration for each memory bank |
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@endverbatim |
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****************************************************************************** |
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*/ |
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/* Includes ------------------------------------------------------------------*/ |
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#include "stm32l4xx_hal.h" |
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/** @addtogroup STM32L4xx_HAL_Driver |
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* @{ |
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*/ |
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#if defined(HAL_NOR_MODULE_ENABLED) || defined(HAL_SRAM_MODULE_ENABLED) || defined(HAL_NAND_MODULE_ENABLED) |
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/** @defgroup FMC_LL FMC Low Layer |
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* @brief FMC driver modules |
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* @{ |
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*/ |
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/* Private typedef -----------------------------------------------------------*/ |
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/* Private define ------------------------------------------------------------*/ |
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/** @defgroup FMC_LL_Private_Constants FMC Low Layer Private Constants |
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* @{ |
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*/ |
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/* ----------------------- FMC registers bit mask --------------------------- */ |
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#if defined(FMC_BANK1) |
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/* --- BCR Register ---*/ |
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/* BCR register clear mask */ |
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/* --- BTR Register ---*/ |
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/* BTR register clear mask */ |
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#if defined(FMC_BTRx_DATAHLD) |
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#define BTR_CLEAR_MASK ((uint32_t)(FMC_BTRx_ADDSET | FMC_BTRx_ADDHLD |\ |
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FMC_BTRx_DATAST | FMC_BTRx_BUSTURN |\ |
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FMC_BTRx_CLKDIV | FMC_BTRx_DATLAT |\ |
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FMC_BTRx_ACCMOD | FMC_BTRx_DATAHLD)) |
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#else |
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#define BTR_CLEAR_MASK ((uint32_t)(FMC_BTRx_ADDSET | FMC_BTRx_ADDHLD |\ |
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FMC_BTRx_DATAST | FMC_BTRx_BUSTURN |\ |
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FMC_BTRx_CLKDIV | FMC_BTRx_DATLAT |\ |
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FMC_BTRx_ACCMOD)) |
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#endif /* FMC_BTRx_DATAHLD */ |
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/* --- BWTR Register ---*/ |
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/* BWTR register clear mask */ |
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#if defined(FMC_BWTRx_DATAHLD) |
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#define BWTR_CLEAR_MASK ((uint32_t)(FMC_BWTRx_ADDSET | FMC_BWTRx_ADDHLD |\ |
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FMC_BWTRx_DATAST | FMC_BWTRx_BUSTURN |\ |
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FMC_BWTRx_ACCMOD | FMC_BWTRx_DATAHLD)) |
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#else |
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#define BWTR_CLEAR_MASK ((uint32_t)(FMC_BWTRx_ADDSET | FMC_BWTRx_ADDHLD |\ |
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FMC_BWTRx_DATAST | FMC_BWTRx_BUSTURN |\ |
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FMC_BWTRx_ACCMOD)) |
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#endif /* FMC_BWTRx_DATAHLD */ |
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#endif /* FMC_BANK1 */ |
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#if defined(FMC_BANK3) |
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|
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/* --- PCR Register ---*/ |
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/* PCR register clear mask */ |
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#define PCR_CLEAR_MASK ((uint32_t)(FMC_PCR_PWAITEN | FMC_PCR_PBKEN | \ |
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FMC_PCR_PTYP | FMC_PCR_PWID | \ |
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FMC_PCR_ECCEN | FMC_PCR_TCLR | \ |
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FMC_PCR_TAR | FMC_PCR_ECCPS)) |
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/* --- PMEM Register ---*/ |
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/* PMEM register clear mask */ |
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#define PMEM_CLEAR_MASK ((uint32_t)(FMC_PMEM_MEMSET | FMC_PMEM_MEMWAIT |\ |
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FMC_PMEM_MEMHOLD | FMC_PMEM_MEMHIZ)) |
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/* --- PATT Register ---*/ |
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/* PATT register clear mask */ |
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#define PATT_CLEAR_MASK ((uint32_t)(FMC_PATT_ATTSET | FMC_PATT_ATTWAIT |\ |
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FMC_PATT_ATTHOLD | FMC_PATT_ATTHIZ)) |
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#endif /* FMC_BANK3 */ |
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/** |
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* @} |
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*/ |
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/* Private macro -------------------------------------------------------------*/ |
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/* Private variables ---------------------------------------------------------*/ |
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/* Private function prototypes -----------------------------------------------*/ |
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/* Exported functions --------------------------------------------------------*/ |
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/** @defgroup FMC_LL_Exported_Functions FMC Low Layer Exported Functions |
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* @{ |
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*/ |
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#if defined(FMC_BANK1) |
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/** @defgroup FMC_LL_Exported_Functions_NORSRAM FMC Low Layer NOR SRAM Exported Functions |
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* @brief NORSRAM Controller functions |
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* |
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@verbatim |
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============================================================================== |
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##### How to use NORSRAM device driver ##### |
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============================================================================== |
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[..] |
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This driver contains a set of APIs to interface with the FMC NORSRAM banks in order |
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to run the NORSRAM external devices. |
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(+) FMC NORSRAM bank reset using the function FMC_NORSRAM_DeInit() |
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(+) FMC NORSRAM bank control configuration using the function FMC_NORSRAM_Init() |
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(+) FMC NORSRAM bank timing configuration using the function FMC_NORSRAM_Timing_Init() |
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(+) FMC NORSRAM bank extended timing configuration using the function |
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FMC_NORSRAM_Extended_Timing_Init() |
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(+) FMC NORSRAM bank enable/disable write operation using the functions |
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FMC_NORSRAM_WriteOperation_Enable()/FMC_NORSRAM_WriteOperation_Disable() |
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@endverbatim |
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* @{ |
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*/ |
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/** @defgroup FMC_LL_NORSRAM_Exported_Functions_Group1 Initialization and de-initialization functions |
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* @brief Initialization and Configuration functions |
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* |
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@verbatim |
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============================================================================== |
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##### Initialization and de_initialization functions ##### |
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============================================================================== |
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[..] |
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This section provides functions allowing to: |
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(+) Initialize and configure the FMC NORSRAM interface |
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(+) De-initialize the FMC NORSRAM interface |
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(+) Configure the FMC clock and associated GPIOs |
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@endverbatim |
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* @{ |
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*/ |
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/** |
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* @brief Initialize the FMC_NORSRAM device according to the specified |
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* control parameters in the FMC_NORSRAM_InitTypeDef |
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* @param Device Pointer to NORSRAM device instance |
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* @param Init Pointer to NORSRAM Initialization structure |
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* @retval HAL status |
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*/ |
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HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device, |
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FMC_NORSRAM_InitTypeDef *Init) |
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{ |
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uint32_t flashaccess; |
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uint32_t btcr_reg; |
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uint32_t mask; |
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/* Check the parameters */ |
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assert_param(IS_FMC_NORSRAM_DEVICE(Device)); |
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assert_param(IS_FMC_NORSRAM_BANK(Init->NSBank)); |
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assert_param(IS_FMC_MUX(Init->DataAddressMux)); |
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assert_param(IS_FMC_MEMORY(Init->MemoryType)); |
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assert_param(IS_FMC_NORSRAM_MEMORY_WIDTH(Init->MemoryDataWidth)); |
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assert_param(IS_FMC_BURSTMODE(Init->BurstAccessMode)); |
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assert_param(IS_FMC_WAIT_POLARITY(Init->WaitSignalPolarity)); |
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assert_param(IS_FMC_WAIT_SIGNAL_ACTIVE(Init->WaitSignalActive)); |
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assert_param(IS_FMC_WRITE_OPERATION(Init->WriteOperation)); |
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assert_param(IS_FMC_WAITE_SIGNAL(Init->WaitSignal)); |
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assert_param(IS_FMC_EXTENDED_MODE(Init->ExtendedMode)); |
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assert_param(IS_FMC_ASYNWAIT(Init->AsynchronousWait)); |
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assert_param(IS_FMC_WRITE_BURST(Init->WriteBurst)); |
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assert_param(IS_FMC_CONTINOUS_CLOCK(Init->ContinuousClock)); |
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#if defined(FMC_BCR1_WFDIS) |
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assert_param(IS_FMC_WRITE_FIFO(Init->WriteFifo)); |
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#endif /* FMC_BCR1_WFDIS */ |
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assert_param(IS_FMC_PAGESIZE(Init->PageSize)); |
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#if defined(FMC_BCRx_NBLSET) |
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assert_param(IS_FMC_NBL_SETUPTIME(Init->NBLSetupTime)); |
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#endif /* FMC_BCRx_NBLSET */ |
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#if defined(FMC_PCSCNTR_CSCOUNT) |
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assert_param(IS_FUNCTIONAL_STATE(Init->MaxChipSelectPulse)); |
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#endif /* FMC_PCSCNTR_CSCOUNT */ |
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/* Disable NORSRAM Device */ |
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__FMC_NORSRAM_DISABLE(Device, Init->NSBank); |
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/* Set NORSRAM device control parameters */ |
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if (Init->MemoryType == FMC_MEMORY_TYPE_NOR) |
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{ |
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flashaccess = FMC_NORSRAM_FLASH_ACCESS_ENABLE; |
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} |
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else |
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{ |
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flashaccess = FMC_NORSRAM_FLASH_ACCESS_DISABLE; |
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} |
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btcr_reg = (flashaccess | \ |
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Init->DataAddressMux | \ |
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Init->MemoryType | \ |
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Init->MemoryDataWidth | \ |
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Init->BurstAccessMode | \ |
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Init->WaitSignalPolarity | \ |
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Init->WaitSignalActive | \ |
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Init->WriteOperation | \ |
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Init->WaitSignal | \ |
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Init->ExtendedMode | \ |
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Init->AsynchronousWait | \ |
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Init->WriteBurst); |
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btcr_reg |= Init->ContinuousClock; |
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#if defined(FMC_BCR1_WFDIS) |
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btcr_reg |= Init->WriteFifo; |
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#endif /* FMC_BCR1_WFDIS */ |
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#if defined(FMC_BCRx_NBLSET) |
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btcr_reg |= Init->NBLSetupTime; |
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#endif /* FMC_BCRx_NBLSET */ |
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btcr_reg |= Init->PageSize; |
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mask = (FMC_BCRx_MBKEN | |
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FMC_BCRx_MUXEN | |
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FMC_BCRx_MTYP | |
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FMC_BCRx_MWID | |
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FMC_BCRx_FACCEN | |
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FMC_BCRx_BURSTEN | |
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FMC_BCRx_WAITPOL | |
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FMC_BCRx_WAITCFG | |
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FMC_BCRx_WREN | |
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FMC_BCRx_WAITEN | |
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FMC_BCRx_EXTMOD | |
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FMC_BCRx_ASYNCWAIT | |
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FMC_BCRx_CBURSTRW); |
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mask |= FMC_BCR1_CCLKEN; |
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#if defined(FMC_BCR1_WFDIS) |
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mask |= FMC_BCR1_WFDIS; |
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#endif /* FMC_BCR1_WFDIS */ |
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#if defined(FMC_BCRx_NBLSET) |
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mask |= FMC_BCRx_NBLSET; |
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#endif /* FMC_BCRx_NBLSET */ |
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mask |= FMC_BCRx_CPSIZE; |
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MODIFY_REG(Device->BTCR[Init->NSBank], mask, btcr_reg); |
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/* Configure synchronous mode when Continuous clock is enabled for bank2..4 */ |
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if ((Init->ContinuousClock == FMC_CONTINUOUS_CLOCK_SYNC_ASYNC) && (Init->NSBank != FMC_NORSRAM_BANK1)) |
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{ |
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MODIFY_REG(Device->BTCR[FMC_NORSRAM_BANK1], FMC_BCR1_CCLKEN, Init->ContinuousClock); |
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} |
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#if defined(FMC_BCR1_WFDIS) |
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if (Init->NSBank != FMC_NORSRAM_BANK1) |
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{ |
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/* Configure Write FIFO mode when Write Fifo is enabled for bank2..4 */ |
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SET_BIT(Device->BTCR[FMC_NORSRAM_BANK1], (uint32_t)(Init->WriteFifo)); |
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} |
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#endif /* FMC_BCR1_WFDIS */ |
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#if defined(FMC_PCSCNTR_CSCOUNT) |
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/* Check PSRAM chip select counter state */ |
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if (Init->MaxChipSelectPulse == ENABLE) |
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{ |
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/* Check the parameters */ |
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assert_param(IS_FMC_MAX_CHIP_SELECT_PULSE_TIME(Init->MaxChipSelectPulseTime)); |
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/* Configure PSRAM chip select counter value */ |
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MODIFY_REG(Device->PCSCNTR, FMC_PCSCNTR_CSCOUNT, (uint32_t)(Init->MaxChipSelectPulseTime)); |
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/* Enable PSRAM chip select counter for the bank */ |
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switch (Init->NSBank) |
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{ |
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case FMC_NORSRAM_BANK1 : |
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SET_BIT(Device->PCSCNTR, FMC_PCSCNTR_CNTB1EN); |
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break; |
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case FMC_NORSRAM_BANK2 : |
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SET_BIT(Device->PCSCNTR, FMC_PCSCNTR_CNTB2EN); |
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break; |
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case FMC_NORSRAM_BANK3 : |
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SET_BIT(Device->PCSCNTR, FMC_PCSCNTR_CNTB3EN); |
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break; |
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default : |
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SET_BIT(Device->PCSCNTR, FMC_PCSCNTR_CNTB4EN); |
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break; |
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} |
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} |
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#endif /* FMC_PCSCNTR_CSCOUNT */ |
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return HAL_OK; |
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} |
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/** |
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* @brief DeInitialize the FMC_NORSRAM peripheral |
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* @param Device Pointer to NORSRAM device instance |
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* @param ExDevice Pointer to NORSRAM extended mode device instance |
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* @param Bank NORSRAM bank number |
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* @retval HAL status |
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*/ |
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HAL_StatusTypeDef FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef *Device, |
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FMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank) |
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{ |
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/* Check the parameters */ |
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assert_param(IS_FMC_NORSRAM_DEVICE(Device)); |
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assert_param(IS_FMC_NORSRAM_EXTENDED_DEVICE(ExDevice)); |
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assert_param(IS_FMC_NORSRAM_BANK(Bank)); |
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/* Disable the FMC_NORSRAM device */ |
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__FMC_NORSRAM_DISABLE(Device, Bank); |
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/* De-initialize the FMC_NORSRAM device */ |
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/* FMC_NORSRAM_BANK1 */ |
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if (Bank == FMC_NORSRAM_BANK1) |
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{ |
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Device->BTCR[Bank] = 0x000030DBU; |
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} |
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/* FMC_NORSRAM_BANK2, FMC_NORSRAM_BANK3 or FMC_NORSRAM_BANK4 */ |
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else |
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{ |
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Device->BTCR[Bank] = 0x000030D2U; |
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} |
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Device->BTCR[Bank + 1U] = 0x0FFFFFFFU; |
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ExDevice->BWTR[Bank] = 0x0FFFFFFFU; |
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#if defined(FMC_PCSCNTR_CSCOUNT) |
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/* De-initialize PSRAM chip select counter */ |
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switch (Bank) |
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{ |
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case FMC_NORSRAM_BANK1 : |
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CLEAR_BIT(Device->PCSCNTR, FMC_PCSCNTR_CNTB1EN); |
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break; |
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case FMC_NORSRAM_BANK2 : |
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CLEAR_BIT(Device->PCSCNTR, FMC_PCSCNTR_CNTB2EN); |
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break; |
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case FMC_NORSRAM_BANK3 : |
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CLEAR_BIT(Device->PCSCNTR, FMC_PCSCNTR_CNTB3EN); |
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break; |
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default : |
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CLEAR_BIT(Device->PCSCNTR, FMC_PCSCNTR_CNTB4EN); |
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break; |
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} |
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#endif /* FMC_PCSCNTR_CSCOUNT */ |
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return HAL_OK; |
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} |
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/** |
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* @brief Initialize the FMC_NORSRAM Timing according to the specified |
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* parameters in the FMC_NORSRAM_TimingTypeDef |
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* @param Device Pointer to NORSRAM device instance |
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* @param Timing Pointer to NORSRAM Timing structure |
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* @param Bank NORSRAM bank number |
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* @retval HAL status |
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*/ |
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HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef *Device, |
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FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank) |
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{ |
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uint32_t tmpr; |
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/* Check the parameters */ |
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assert_param(IS_FMC_NORSRAM_DEVICE(Device)); |
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assert_param(IS_FMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime)); |
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assert_param(IS_FMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime)); |
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#if defined(FMC_BTRx_DATAHLD) |
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assert_param(IS_FMC_DATAHOLD_DURATION(Timing->DataHoldTime)); |
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#endif /* FMC_BTRx_DATAHLD */ |
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assert_param(IS_FMC_DATASETUP_TIME(Timing->DataSetupTime)); |
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assert_param(IS_FMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration)); |
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assert_param(IS_FMC_CLK_DIV(Timing->CLKDivision)); |
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assert_param(IS_FMC_DATA_LATENCY(Timing->DataLatency)); |
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assert_param(IS_FMC_ACCESS_MODE(Timing->AccessMode)); |
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assert_param(IS_FMC_NORSRAM_BANK(Bank)); |
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|
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/* Set FMC_NORSRAM device timing parameters */ |
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#if defined(FMC_BTRx_DATAHLD) |
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MODIFY_REG(Device->BTCR[Bank + 1U], BTR_CLEAR_MASK, (Timing->AddressSetupTime | |
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((Timing->AddressHoldTime) << FMC_BTRx_ADDHLD_Pos) | |
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((Timing->DataSetupTime) << FMC_BTRx_DATAST_Pos) | |
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((Timing->DataHoldTime) << FMC_BTRx_DATAHLD_Pos) | |
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((Timing->BusTurnAroundDuration) << FMC_BTRx_BUSTURN_Pos) | |
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(((Timing->CLKDivision) - 1U) << FMC_BTRx_CLKDIV_Pos) | |
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(((Timing->DataLatency) - 2U) << FMC_BTRx_DATLAT_Pos) | |
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(Timing->AccessMode))); |
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#else /* FMC_BTRx_DATAHLD */ |
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MODIFY_REG(Device->BTCR[Bank + 1U], BTR_CLEAR_MASK, (Timing->AddressSetupTime | |
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((Timing->AddressHoldTime) << FMC_BTRx_ADDHLD_Pos) | |
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((Timing->DataSetupTime) << FMC_BTRx_DATAST_Pos) | |
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((Timing->BusTurnAroundDuration) << FMC_BTRx_BUSTURN_Pos) | |
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(((Timing->CLKDivision) - 1U) << FMC_BTRx_CLKDIV_Pos) | |
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(((Timing->DataLatency) - 2U) << FMC_BTRx_DATLAT_Pos) | |
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(Timing->AccessMode))); |
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#endif /* FMC_BTRx_DATAHLD */ |
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/* Configure Clock division value (in NORSRAM bank 1) when continuous clock is enabled */ |
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if (HAL_IS_BIT_SET(Device->BTCR[FMC_NORSRAM_BANK1], FMC_BCR1_CCLKEN)) |
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{ |
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tmpr = (uint32_t)(Device->BTCR[FMC_NORSRAM_BANK1 + 1U] & ~((0x0FU) << FMC_BTRx_CLKDIV_Pos)); |
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tmpr |= (uint32_t)(((Timing->CLKDivision) - 1U) << FMC_BTRx_CLKDIV_Pos); |
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MODIFY_REG(Device->BTCR[FMC_NORSRAM_BANK1 + 1U], FMC_BTRx_CLKDIV, tmpr); |
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} |
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return HAL_OK; |
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} |
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/** |
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* @brief Initialize the FMC_NORSRAM Extended mode Timing according to the specified |
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* parameters in the FMC_NORSRAM_TimingTypeDef |
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* @param Device Pointer to NORSRAM device instance |
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* @param Timing Pointer to NORSRAM Timing structure |
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* @param Bank NORSRAM bank number |
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* @param ExtendedMode FMC Extended Mode |
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* This parameter can be one of the following values: |
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* @arg FMC_EXTENDED_MODE_DISABLE |
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* @arg FMC_EXTENDED_MODE_ENABLE |
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* @retval HAL status |
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*/ |
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HAL_StatusTypeDef FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef *Device, |
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FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, |
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uint32_t ExtendedMode) |
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{ |
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/* Check the parameters */ |
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assert_param(IS_FMC_EXTENDED_MODE(ExtendedMode)); |
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|
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/* Set NORSRAM device timing register for write configuration, if extended mode is used */ |
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if (ExtendedMode == FMC_EXTENDED_MODE_ENABLE) |
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{ |
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/* Check the parameters */ |
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assert_param(IS_FMC_NORSRAM_EXTENDED_DEVICE(Device)); |
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assert_param(IS_FMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime)); |
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assert_param(IS_FMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime)); |
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assert_param(IS_FMC_DATASETUP_TIME(Timing->DataSetupTime)); |
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#if defined(FMC_BTRx_DATAHLD) |
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assert_param(IS_FMC_DATAHOLD_DURATION(Timing->DataHoldTime)); |
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#endif /* FMC_BTRx_DATAHLD */ |
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assert_param(IS_FMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration)); |
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assert_param(IS_FMC_ACCESS_MODE(Timing->AccessMode)); |
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assert_param(IS_FMC_NORSRAM_BANK(Bank)); |
|
|
|
/* Set NORSRAM device timing register for write configuration, if extended mode is used */ |
|
#if defined(FMC_BTRx_DATAHLD) |
|
MODIFY_REG(Device->BWTR[Bank], BWTR_CLEAR_MASK, (Timing->AddressSetupTime | |
|
((Timing->AddressHoldTime) << FMC_BWTRx_ADDHLD_Pos) | |
|
((Timing->DataSetupTime) << FMC_BWTRx_DATAST_Pos) | |
|
((Timing->DataHoldTime) << FMC_BWTRx_DATAHLD_Pos) | |
|
Timing->AccessMode | |
|
((Timing->BusTurnAroundDuration) << FMC_BWTRx_BUSTURN_Pos))); |
|
#else /* FMC_BTRx_DATAHLD */ |
|
MODIFY_REG(Device->BWTR[Bank], BWTR_CLEAR_MASK, (Timing->AddressSetupTime | |
|
((Timing->AddressHoldTime) << FMC_BWTRx_ADDHLD_Pos) | |
|
((Timing->DataSetupTime) << FMC_BWTRx_DATAST_Pos) | |
|
Timing->AccessMode | |
|
((Timing->BusTurnAroundDuration) << FMC_BWTRx_BUSTURN_Pos))); |
|
#endif /* FMC_BTRx_DATAHLD */ |
|
} |
|
else |
|
{ |
|
Device->BWTR[Bank] = 0x0FFFFFFFU; |
|
} |
|
|
|
return HAL_OK; |
|
} |
|
/** |
|
* @} |
|
*/ |
|
|
|
/** @addtogroup FMC_LL_NORSRAM_Private_Functions_Group2 |
|
* @brief management functions |
|
* |
|
@verbatim |
|
============================================================================== |
|
##### FMC_NORSRAM Control functions ##### |
|
============================================================================== |
|
[..] |
|
This subsection provides a set of functions allowing to control dynamically |
|
the FMC NORSRAM interface. |
|
|
|
@endverbatim |
|
* @{ |
|
*/ |
|
|
|
/** |
|
* @brief Enables dynamically FMC_NORSRAM write operation. |
|
* @param Device Pointer to NORSRAM device instance |
|
* @param Bank NORSRAM bank number |
|
* @retval HAL status |
|
*/ |
|
HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Enable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank) |
|
{ |
|
/* Check the parameters */ |
|
assert_param(IS_FMC_NORSRAM_DEVICE(Device)); |
|
assert_param(IS_FMC_NORSRAM_BANK(Bank)); |
|
|
|
/* Enable write operation */ |
|
SET_BIT(Device->BTCR[Bank], FMC_WRITE_OPERATION_ENABLE); |
|
|
|
return HAL_OK; |
|
} |
|
|
|
/** |
|
* @brief Disables dynamically FMC_NORSRAM write operation. |
|
* @param Device Pointer to NORSRAM device instance |
|
* @param Bank NORSRAM bank number |
|
* @retval HAL status |
|
*/ |
|
HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Disable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank) |
|
{ |
|
/* Check the parameters */ |
|
assert_param(IS_FMC_NORSRAM_DEVICE(Device)); |
|
assert_param(IS_FMC_NORSRAM_BANK(Bank)); |
|
|
|
/* Disable write operation */ |
|
CLEAR_BIT(Device->BTCR[Bank], FMC_WRITE_OPERATION_ENABLE); |
|
|
|
return HAL_OK; |
|
} |
|
|
|
/** |
|
* @} |
|
*/ |
|
|
|
/** |
|
* @} |
|
*/ |
|
#endif /* FMC_BANK1 */ |
|
|
|
#if defined(FMC_BANK3) |
|
|
|
/** @defgroup FMC_LL_Exported_Functions_NAND FMC Low Layer NAND Exported Functions |
|
* @brief NAND Controller functions |
|
* |
|
@verbatim |
|
============================================================================== |
|
##### How to use NAND device driver ##### |
|
============================================================================== |
|
[..] |
|
This driver contains a set of APIs to interface with the FMC NAND banks in order |
|
to run the NAND external devices. |
|
|
|
(+) FMC NAND bank reset using the function FMC_NAND_DeInit() |
|
(+) FMC NAND bank control configuration using the function FMC_NAND_Init() |
|
(+) FMC NAND bank common space timing configuration using the function |
|
FMC_NAND_CommonSpace_Timing_Init() |
|
(+) FMC NAND bank attribute space timing configuration using the function |
|
FMC_NAND_AttributeSpace_Timing_Init() |
|
(+) FMC NAND bank enable/disable ECC correction feature using the functions |
|
FMC_NAND_ECC_Enable()/FMC_NAND_ECC_Disable() |
|
(+) FMC NAND bank get ECC correction code using the function FMC_NAND_GetECC() |
|
|
|
@endverbatim |
|
* @{ |
|
*/ |
|
|
|
/** @defgroup FMC_LL_NAND_Exported_Functions_Group1 Initialization and de-initialization functions |
|
* @brief Initialization and Configuration functions |
|
* |
|
@verbatim |
|
============================================================================== |
|
##### Initialization and de_initialization functions ##### |
|
============================================================================== |
|
[..] |
|
This section provides functions allowing to: |
|
(+) Initialize and configure the FMC NAND interface |
|
(+) De-initialize the FMC NAND interface |
|
(+) Configure the FMC clock and associated GPIOs |
|
|
|
@endverbatim |
|
* @{ |
|
*/ |
|
|
|
/** |
|
* @brief Initializes the FMC_NAND device according to the specified |
|
* control parameters in the FMC_NAND_HandleTypeDef |
|
* @param Device Pointer to NAND device instance |
|
* @param Init Pointer to NAND Initialization structure |
|
* @retval HAL status |
|
*/ |
|
HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef *Device, FMC_NAND_InitTypeDef *Init) |
|
{ |
|
/* Check the parameters */ |
|
assert_param(IS_FMC_NAND_DEVICE(Device)); |
|
assert_param(IS_FMC_NAND_BANK(Init->NandBank)); |
|
assert_param(IS_FMC_WAIT_FEATURE(Init->Waitfeature)); |
|
assert_param(IS_FMC_NAND_MEMORY_WIDTH(Init->MemoryDataWidth)); |
|
assert_param(IS_FMC_ECC_STATE(Init->EccComputation)); |
|
assert_param(IS_FMC_ECCPAGE_SIZE(Init->ECCPageSize)); |
|
assert_param(IS_FMC_TCLR_TIME(Init->TCLRSetupTime)); |
|
assert_param(IS_FMC_TAR_TIME(Init->TARSetupTime)); |
|
|
|
/* NAND bank 3 registers configuration */ |
|
MODIFY_REG(Device->PCR, PCR_CLEAR_MASK, (Init->Waitfeature | |
|
FMC_PCR_MEMORY_TYPE_NAND | |
|
Init->MemoryDataWidth | |
|
Init->EccComputation | |
|
Init->ECCPageSize | |
|
((Init->TCLRSetupTime) << FMC_PCR_TCLR_Pos) | |
|
((Init->TARSetupTime) << FMC_PCR_TAR_Pos))); |
|
|
|
return HAL_OK; |
|
} |
|
|
|
/** |
|
* @brief Initializes the FMC_NAND Common space Timing according to the specified |
|
* parameters in the FMC_NAND_PCC_TimingTypeDef |
|
* @param Device Pointer to NAND device instance |
|
* @param Timing Pointer to NAND timing structure |
|
* @param Bank NAND bank number |
|
* @retval HAL status |
|
*/ |
|
HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef *Device, |
|
FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank) |
|
{ |
|
/* Check the parameters */ |
|
assert_param(IS_FMC_NAND_DEVICE(Device)); |
|
assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime)); |
|
assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime)); |
|
assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime)); |
|
assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime)); |
|
assert_param(IS_FMC_NAND_BANK(Bank)); |
|
|
|
/* Prevent unused argument(s) compilation warning if no assert_param check */ |
|
UNUSED(Bank); |
|
|
|
/* NAND bank 3 registers configuration */ |
|
MODIFY_REG(Device->PMEM, PMEM_CLEAR_MASK, (Timing->SetupTime | |
|
((Timing->WaitSetupTime) << FMC_PMEM_MEMWAIT_Pos) | |
|
((Timing->HoldSetupTime) << FMC_PMEM_MEMHOLD_Pos) | |
|
((Timing->HiZSetupTime) << FMC_PMEM_MEMHIZ_Pos))); |
|
|
|
return HAL_OK; |
|
} |
|
|
|
/** |
|
* @brief Initializes the FMC_NAND Attribute space Timing according to the specified |
|
* parameters in the FMC_NAND_PCC_TimingTypeDef |
|
* @param Device Pointer to NAND device instance |
|
* @param Timing Pointer to NAND timing structure |
|
* @param Bank NAND bank number |
|
* @retval HAL status |
|
*/ |
|
HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef *Device, |
|
FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank) |
|
{ |
|
/* Check the parameters */ |
|
assert_param(IS_FMC_NAND_DEVICE(Device)); |
|
assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime)); |
|
assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime)); |
|
assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime)); |
|
assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime)); |
|
assert_param(IS_FMC_NAND_BANK(Bank)); |
|
|
|
/* Prevent unused argument(s) compilation warning if no assert_param check */ |
|
UNUSED(Bank); |
|
|
|
/* NAND bank 3 registers configuration */ |
|
MODIFY_REG(Device->PATT, PATT_CLEAR_MASK, (Timing->SetupTime | |
|
((Timing->WaitSetupTime) << FMC_PATT_ATTWAIT_Pos) | |
|
((Timing->HoldSetupTime) << FMC_PATT_ATTHOLD_Pos) | |
|
((Timing->HiZSetupTime) << FMC_PATT_ATTHIZ_Pos))); |
|
|
|
return HAL_OK; |
|
} |
|
|
|
/** |
|
* @brief DeInitializes the FMC_NAND device |
|
* @param Device Pointer to NAND device instance |
|
* @param Bank NAND bank number |
|
* @retval HAL status |
|
*/ |
|
HAL_StatusTypeDef FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank) |
|
{ |
|
/* Check the parameters */ |
|
assert_param(IS_FMC_NAND_DEVICE(Device)); |
|
assert_param(IS_FMC_NAND_BANK(Bank)); |
|
|
|
/* Disable the NAND Bank */ |
|
__FMC_NAND_DISABLE(Device, Bank); |
|
|
|
/* De-initialize the NAND Bank */ |
|
/* Prevent unused argument(s) compilation warning if no assert_param check */ |
|
UNUSED(Bank); |
|
|
|
/* Set the FMC_NAND_BANK3 registers to their reset values */ |
|
WRITE_REG(Device->PCR, 0x00000018U); |
|
WRITE_REG(Device->SR, 0x00000040U); |
|
WRITE_REG(Device->PMEM, 0xFCFCFCFCU); |
|
WRITE_REG(Device->PATT, 0xFCFCFCFCU); |
|
|
|
return HAL_OK; |
|
} |
|
|
|
/** |
|
* @} |
|
*/ |
|
|
|
/** @defgroup HAL_FMC_NAND_Group2 Peripheral Control functions |
|
* @brief management functions |
|
* |
|
@verbatim |
|
============================================================================== |
|
##### FMC_NAND Control functions ##### |
|
============================================================================== |
|
[..] |
|
This subsection provides a set of functions allowing to control dynamically |
|
the FMC NAND interface. |
|
|
|
@endverbatim |
|
* @{ |
|
*/ |
|
|
|
|
|
/** |
|
* @brief Enables dynamically FMC_NAND ECC feature. |
|
* @param Device Pointer to NAND device instance |
|
* @param Bank NAND bank number |
|
* @retval HAL status |
|
*/ |
|
HAL_StatusTypeDef FMC_NAND_ECC_Enable(FMC_NAND_TypeDef *Device, uint32_t Bank) |
|
{ |
|
/* Check the parameters */ |
|
assert_param(IS_FMC_NAND_DEVICE(Device)); |
|
assert_param(IS_FMC_NAND_BANK(Bank)); |
|
|
|
/* Enable ECC feature */ |
|
/* Prevent unused argument(s) compilation warning if no assert_param check */ |
|
UNUSED(Bank); |
|
|
|
SET_BIT(Device->PCR, FMC_PCR_ECCEN); |
|
|
|
return HAL_OK; |
|
} |
|
|
|
|
|
/** |
|
* @brief Disables dynamically FMC_NAND ECC feature. |
|
* @param Device Pointer to NAND device instance |
|
* @param Bank NAND bank number |
|
* @retval HAL status |
|
*/ |
|
HAL_StatusTypeDef FMC_NAND_ECC_Disable(FMC_NAND_TypeDef *Device, uint32_t Bank) |
|
{ |
|
/* Check the parameters */ |
|
assert_param(IS_FMC_NAND_DEVICE(Device)); |
|
assert_param(IS_FMC_NAND_BANK(Bank)); |
|
|
|
/* Disable ECC feature */ |
|
/* Prevent unused argument(s) compilation warning if no assert_param check */ |
|
UNUSED(Bank); |
|
|
|
CLEAR_BIT(Device->PCR, FMC_PCR_ECCEN); |
|
|
|
return HAL_OK; |
|
} |
|
|
|
/** |
|
* @brief Disables dynamically FMC_NAND ECC feature. |
|
* @param Device Pointer to NAND device instance |
|
* @param ECCval Pointer to ECC value |
|
* @param Bank NAND bank number |
|
* @param Timeout Timeout wait value |
|
* @retval HAL status |
|
*/ |
|
HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, |
|
uint32_t Timeout) |
|
{ |
|
uint32_t tickstart; |
|
|
|
/* Check the parameters */ |
|
assert_param(IS_FMC_NAND_DEVICE(Device)); |
|
assert_param(IS_FMC_NAND_BANK(Bank)); |
|
|
|
/* Get tick */ |
|
tickstart = HAL_GetTick(); |
|
|
|
/* Wait until FIFO is empty */ |
|
while (__FMC_NAND_GET_FLAG(Device, Bank, FMC_FLAG_FEMPT) == RESET) |
|
{ |
|
/* Check for the Timeout */ |
|
if (Timeout != HAL_MAX_DELAY) |
|
{ |
|
if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) |
|
{ |
|
return HAL_TIMEOUT; |
|
} |
|
} |
|
} |
|
|
|
/* Prevent unused argument(s) compilation warning if no assert_param check */ |
|
UNUSED(Bank); |
|
|
|
/* Get the ECCR register value */ |
|
*ECCval = (uint32_t)Device->ECCR; |
|
|
|
return HAL_OK; |
|
} |
|
|
|
/** |
|
* @} |
|
*/ |
|
#endif /* FMC_BANK3 */ |
|
|
|
|
|
|
|
/** |
|
* @} |
|
*/ |
|
|
|
/** |
|
* @} |
|
*/ |
|
|
|
#endif /* HAL_NOR_MODULE_ENABLED */ |
|
/** |
|
* @} |
|
*/ |
|
/** |
|
* @} |
|
*/
|
|
|