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502 lines
19 KiB
502 lines
19 KiB
/** |
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****************************************************************************** |
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* @file stm32f4xx_hal_cortex.c |
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* @author MCD Application Team |
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* @brief CORTEX HAL module driver. |
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* This file provides firmware functions to manage the following |
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* functionalities of the CORTEX: |
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* + Initialization and de-initialization functions |
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* + Peripheral Control functions |
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* |
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@verbatim |
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============================================================================== |
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##### How to use this driver ##### |
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============================================================================== |
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[..] |
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*** How to configure Interrupts using CORTEX HAL driver *** |
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=========================================================== |
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[..] |
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This section provides functions allowing to configure the NVIC interrupts (IRQ). |
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The Cortex-M4 exceptions are managed by CMSIS functions. |
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(#) Configure the NVIC Priority Grouping using HAL_NVIC_SetPriorityGrouping() |
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function according to the following table. |
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(#) Configure the priority of the selected IRQ Channels using HAL_NVIC_SetPriority(). |
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(#) Enable the selected IRQ Channels using HAL_NVIC_EnableIRQ(). |
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(#) please refer to programming manual for details in how to configure priority. |
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-@- When the NVIC_PRIORITYGROUP_0 is selected, IRQ preemption is no more possible. |
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The pending IRQ priority will be managed only by the sub priority. |
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-@- IRQ priority order (sorted by highest to lowest priority): |
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(+@) Lowest preemption priority |
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(+@) Lowest sub priority |
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(+@) Lowest hardware priority (IRQ number) |
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[..] |
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*** How to configure Systick using CORTEX HAL driver *** |
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======================================================== |
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[..] |
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Setup SysTick Timer for time base. |
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(+) The HAL_SYSTICK_Config() function calls the SysTick_Config() function which |
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is a CMSIS function that: |
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(++) Configures the SysTick Reload register with value passed as function parameter. |
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(++) Configures the SysTick IRQ priority to the lowest value 0x0F. |
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(++) Resets the SysTick Counter register. |
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(++) Configures the SysTick Counter clock source to be Core Clock Source (HCLK). |
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(++) Enables the SysTick Interrupt. |
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(++) Starts the SysTick Counter. |
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(+) You can change the SysTick Clock source to be HCLK_Div8 by calling the macro |
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__HAL_CORTEX_SYSTICKCLK_CONFIG(SYSTICK_CLKSOURCE_HCLK_DIV8) just after the |
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HAL_SYSTICK_Config() function call. The __HAL_CORTEX_SYSTICKCLK_CONFIG() macro is defined |
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inside the stm32f4xx_hal_cortex.h file. |
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(+) You can change the SysTick IRQ priority by calling the |
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HAL_NVIC_SetPriority(SysTick_IRQn,...) function just after the HAL_SYSTICK_Config() function |
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call. The HAL_NVIC_SetPriority() call the NVIC_SetPriority() function which is a CMSIS function. |
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(+) To adjust the SysTick time base, use the following formula: |
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Reload Value = SysTick Counter Clock (Hz) x Desired Time base (s) |
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(++) Reload Value is the parameter to be passed for HAL_SYSTICK_Config() function |
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(++) Reload Value should not exceed 0xFFFFFF |
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@endverbatim |
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****************************************************************************** |
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* @attention |
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* |
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* Copyright (c) 2017 STMicroelectronics. |
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* All rights reserved. |
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* |
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* This software is licensed under terms that can be found in the LICENSE file in |
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* the root directory of this software component. |
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* If no LICENSE file comes with this software, it is provided AS-IS. |
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****************************************************************************** |
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*/ |
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/* Includes ------------------------------------------------------------------*/ |
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#include "stm32f4xx_hal.h" |
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/** @addtogroup STM32F4xx_HAL_Driver |
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* @{ |
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*/ |
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/** @defgroup CORTEX CORTEX |
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* @brief CORTEX HAL module driver |
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* @{ |
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*/ |
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#ifdef HAL_CORTEX_MODULE_ENABLED |
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/* Private types -------------------------------------------------------------*/ |
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/* Private variables ---------------------------------------------------------*/ |
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/* Private constants ---------------------------------------------------------*/ |
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/* Private macros ------------------------------------------------------------*/ |
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/* Private functions ---------------------------------------------------------*/ |
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/* Exported functions --------------------------------------------------------*/ |
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/** @defgroup CORTEX_Exported_Functions CORTEX Exported Functions |
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* @{ |
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*/ |
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/** @defgroup CORTEX_Exported_Functions_Group1 Initialization and de-initialization functions |
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* @brief Initialization and Configuration functions |
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* |
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@verbatim |
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============================================================================== |
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##### Initialization and de-initialization functions ##### |
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============================================================================== |
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[..] |
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This section provides the CORTEX HAL driver functions allowing to configure Interrupts |
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Systick functionalities |
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@endverbatim |
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* @{ |
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*/ |
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/** |
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* @brief Sets the priority grouping field (preemption priority and subpriority) |
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* using the required unlock sequence. |
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* @param PriorityGroup The priority grouping bits length. |
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* This parameter can be one of the following values: |
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* @arg NVIC_PRIORITYGROUP_0: 0 bits for preemption priority |
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* 4 bits for subpriority |
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* @arg NVIC_PRIORITYGROUP_1: 1 bits for preemption priority |
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* 3 bits for subpriority |
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* @arg NVIC_PRIORITYGROUP_2: 2 bits for preemption priority |
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* 2 bits for subpriority |
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* @arg NVIC_PRIORITYGROUP_3: 3 bits for preemption priority |
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* 1 bits for subpriority |
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* @arg NVIC_PRIORITYGROUP_4: 4 bits for preemption priority |
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* 0 bits for subpriority |
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* @note When the NVIC_PriorityGroup_0 is selected, IRQ preemption is no more possible. |
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* The pending IRQ priority will be managed only by the subpriority. |
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* @retval None |
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*/ |
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void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup) |
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{ |
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/* Check the parameters */ |
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assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup)); |
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/* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */ |
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NVIC_SetPriorityGrouping(PriorityGroup); |
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} |
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/** |
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* @brief Sets the priority of an interrupt. |
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* @param IRQn External interrupt number. |
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* This parameter can be an enumerator of IRQn_Type enumeration |
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* (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f4xxxx.h)) |
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* @param PreemptPriority The preemption priority for the IRQn channel. |
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* This parameter can be a value between 0 and 15 |
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* A lower priority value indicates a higher priority |
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* @param SubPriority the subpriority level for the IRQ channel. |
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* This parameter can be a value between 0 and 15 |
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* A lower priority value indicates a higher priority. |
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* @retval None |
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*/ |
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void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority) |
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{ |
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uint32_t prioritygroup = 0x00U; |
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/* Check the parameters */ |
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assert_param(IS_NVIC_SUB_PRIORITY(SubPriority)); |
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assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority)); |
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prioritygroup = NVIC_GetPriorityGrouping(); |
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NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority)); |
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} |
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/** |
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* @brief Enables a device specific interrupt in the NVIC interrupt controller. |
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* @note To configure interrupts priority correctly, the NVIC_PriorityGroupConfig() |
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* function should be called before. |
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* @param IRQn External interrupt number. |
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* This parameter can be an enumerator of IRQn_Type enumeration |
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* (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f4xxxx.h)) |
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* @retval None |
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*/ |
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void HAL_NVIC_EnableIRQ(IRQn_Type IRQn) |
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{ |
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/* Check the parameters */ |
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assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); |
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/* Enable interrupt */ |
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NVIC_EnableIRQ(IRQn); |
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} |
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/** |
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* @brief Disables a device specific interrupt in the NVIC interrupt controller. |
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* @param IRQn External interrupt number. |
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* This parameter can be an enumerator of IRQn_Type enumeration |
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* (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f4xxxx.h)) |
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* @retval None |
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*/ |
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void HAL_NVIC_DisableIRQ(IRQn_Type IRQn) |
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{ |
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/* Check the parameters */ |
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assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); |
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/* Disable interrupt */ |
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NVIC_DisableIRQ(IRQn); |
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} |
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/** |
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* @brief Initiates a system reset request to reset the MCU. |
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* @retval None |
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*/ |
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void HAL_NVIC_SystemReset(void) |
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{ |
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/* System Reset */ |
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NVIC_SystemReset(); |
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} |
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/** |
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* @brief Initializes the System Timer and its interrupt, and starts the System Tick Timer. |
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* Counter is in free running mode to generate periodic interrupts. |
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* @param TicksNumb Specifies the ticks Number of ticks between two interrupts. |
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* @retval status: - 0 Function succeeded. |
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* - 1 Function failed. |
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*/ |
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uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb) |
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{ |
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return SysTick_Config(TicksNumb); |
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} |
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/** |
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* @} |
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*/ |
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/** @defgroup CORTEX_Exported_Functions_Group2 Peripheral Control functions |
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* @brief Cortex control functions |
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* |
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@verbatim |
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============================================================================== |
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##### Peripheral Control functions ##### |
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============================================================================== |
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[..] |
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This subsection provides a set of functions allowing to control the CORTEX |
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(NVIC, SYSTICK, MPU) functionalities. |
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@endverbatim |
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* @{ |
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*/ |
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#if (__MPU_PRESENT == 1U) |
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/** |
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* @brief Disables the MPU |
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* @retval None |
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*/ |
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void HAL_MPU_Disable(void) |
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{ |
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/* Make sure outstanding transfers are done */ |
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__DMB(); |
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/* Disable fault exceptions */ |
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SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; |
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/* Disable the MPU and clear the control register*/ |
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MPU->CTRL = 0U; |
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} |
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/** |
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* @brief Enable the MPU. |
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* @param MPU_Control Specifies the control mode of the MPU during hard fault, |
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* NMI, FAULTMASK and privileged access to the default memory |
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* This parameter can be one of the following values: |
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* @arg MPU_HFNMI_PRIVDEF_NONE |
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* @arg MPU_HARDFAULT_NMI |
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* @arg MPU_PRIVILEGED_DEFAULT |
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* @arg MPU_HFNMI_PRIVDEF |
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* @retval None |
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*/ |
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void HAL_MPU_Enable(uint32_t MPU_Control) |
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{ |
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/* Enable the MPU */ |
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MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; |
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/* Enable fault exceptions */ |
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SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; |
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/* Ensure MPU setting take effects */ |
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__DSB(); |
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__ISB(); |
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} |
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/** |
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* @brief Initializes and configures the Region and the memory to be protected. |
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* @param MPU_Init Pointer to a MPU_Region_InitTypeDef structure that contains |
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* the initialization and configuration information. |
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* @retval None |
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*/ |
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void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init) |
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{ |
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/* Check the parameters */ |
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assert_param(IS_MPU_REGION_NUMBER(MPU_Init->Number)); |
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assert_param(IS_MPU_REGION_ENABLE(MPU_Init->Enable)); |
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/* Set the Region number */ |
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MPU->RNR = MPU_Init->Number; |
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if ((MPU_Init->Enable) != RESET) |
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{ |
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/* Check the parameters */ |
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assert_param(IS_MPU_INSTRUCTION_ACCESS(MPU_Init->DisableExec)); |
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assert_param(IS_MPU_REGION_PERMISSION_ATTRIBUTE(MPU_Init->AccessPermission)); |
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assert_param(IS_MPU_TEX_LEVEL(MPU_Init->TypeExtField)); |
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assert_param(IS_MPU_ACCESS_SHAREABLE(MPU_Init->IsShareable)); |
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assert_param(IS_MPU_ACCESS_CACHEABLE(MPU_Init->IsCacheable)); |
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assert_param(IS_MPU_ACCESS_BUFFERABLE(MPU_Init->IsBufferable)); |
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assert_param(IS_MPU_SUB_REGION_DISABLE(MPU_Init->SubRegionDisable)); |
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assert_param(IS_MPU_REGION_SIZE(MPU_Init->Size)); |
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MPU->RBAR = MPU_Init->BaseAddress; |
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MPU->RASR = ((uint32_t)MPU_Init->DisableExec << MPU_RASR_XN_Pos) | |
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((uint32_t)MPU_Init->AccessPermission << MPU_RASR_AP_Pos) | |
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((uint32_t)MPU_Init->TypeExtField << MPU_RASR_TEX_Pos) | |
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((uint32_t)MPU_Init->IsShareable << MPU_RASR_S_Pos) | |
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((uint32_t)MPU_Init->IsCacheable << MPU_RASR_C_Pos) | |
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((uint32_t)MPU_Init->IsBufferable << MPU_RASR_B_Pos) | |
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((uint32_t)MPU_Init->SubRegionDisable << MPU_RASR_SRD_Pos) | |
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((uint32_t)MPU_Init->Size << MPU_RASR_SIZE_Pos) | |
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((uint32_t)MPU_Init->Enable << MPU_RASR_ENABLE_Pos); |
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} |
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else |
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{ |
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MPU->RBAR = 0x00U; |
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MPU->RASR = 0x00U; |
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} |
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} |
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#endif /* __MPU_PRESENT */ |
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/** |
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* @brief Gets the priority grouping field from the NVIC Interrupt Controller. |
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* @retval Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field) |
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*/ |
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uint32_t HAL_NVIC_GetPriorityGrouping(void) |
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{ |
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/* Get the PRIGROUP[10:8] field value */ |
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return NVIC_GetPriorityGrouping(); |
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} |
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/** |
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* @brief Gets the priority of an interrupt. |
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* @param IRQn External interrupt number. |
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* This parameter can be an enumerator of IRQn_Type enumeration |
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* (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f4xxxx.h)) |
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* @param PriorityGroup the priority grouping bits length. |
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* This parameter can be one of the following values: |
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* @arg NVIC_PRIORITYGROUP_0: 0 bits for preemption priority |
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* 4 bits for subpriority |
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* @arg NVIC_PRIORITYGROUP_1: 1 bits for preemption priority |
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* 3 bits for subpriority |
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* @arg NVIC_PRIORITYGROUP_2: 2 bits for preemption priority |
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* 2 bits for subpriority |
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* @arg NVIC_PRIORITYGROUP_3: 3 bits for preemption priority |
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* 1 bits for subpriority |
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* @arg NVIC_PRIORITYGROUP_4: 4 bits for preemption priority |
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* 0 bits for subpriority |
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* @param pPreemptPriority Pointer on the Preemptive priority value (starting from 0). |
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* @param pSubPriority Pointer on the Subpriority value (starting from 0). |
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* @retval None |
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*/ |
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void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t *pPreemptPriority, uint32_t *pSubPriority) |
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{ |
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/* Check the parameters */ |
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assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup)); |
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/* Get priority for Cortex-M system or device specific interrupts */ |
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NVIC_DecodePriority(NVIC_GetPriority(IRQn), PriorityGroup, pPreemptPriority, pSubPriority); |
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} |
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/** |
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* @brief Sets Pending bit of an external interrupt. |
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* @param IRQn External interrupt number |
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* This parameter can be an enumerator of IRQn_Type enumeration |
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* (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f4xxxx.h)) |
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* @retval None |
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*/ |
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void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn) |
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{ |
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/* Check the parameters */ |
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assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); |
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/* Set interrupt pending */ |
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NVIC_SetPendingIRQ(IRQn); |
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} |
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/** |
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* @brief Gets Pending Interrupt (reads the pending register in the NVIC |
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* and returns the pending bit for the specified interrupt). |
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* @param IRQn External interrupt number. |
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* This parameter can be an enumerator of IRQn_Type enumeration |
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* (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f4xxxx.h)) |
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* @retval status: - 0 Interrupt status is not pending. |
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* - 1 Interrupt status is pending. |
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*/ |
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uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn) |
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{ |
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/* Check the parameters */ |
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assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); |
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/* Return 1 if pending else 0 */ |
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return NVIC_GetPendingIRQ(IRQn); |
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} |
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/** |
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* @brief Clears the pending bit of an external interrupt. |
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* @param IRQn External interrupt number. |
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* This parameter can be an enumerator of IRQn_Type enumeration |
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* (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f4xxxx.h)) |
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* @retval None |
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*/ |
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void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn) |
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{ |
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/* Check the parameters */ |
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assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); |
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/* Clear pending interrupt */ |
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NVIC_ClearPendingIRQ(IRQn); |
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} |
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/** |
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* @brief Gets active interrupt ( reads the active register in NVIC and returns the active bit). |
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* @param IRQn External interrupt number |
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* This parameter can be an enumerator of IRQn_Type enumeration |
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* (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f4xxxx.h)) |
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* @retval status: - 0 Interrupt status is not pending. |
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* - 1 Interrupt status is pending. |
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*/ |
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uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn) |
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{ |
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/* Check the parameters */ |
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assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); |
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/* Return 1 if active else 0 */ |
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return NVIC_GetActive(IRQn); |
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} |
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/** |
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* @brief Configures the SysTick clock source. |
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* @param CLKSource specifies the SysTick clock source. |
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* This parameter can be one of the following values: |
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* @arg SYSTICK_CLKSOURCE_HCLK_DIV8: AHB clock divided by 8 selected as SysTick clock source. |
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* @arg SYSTICK_CLKSOURCE_HCLK: AHB clock selected as SysTick clock source. |
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* @retval None |
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*/ |
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void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource) |
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{ |
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/* Check the parameters */ |
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assert_param(IS_SYSTICK_CLK_SOURCE(CLKSource)); |
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if (CLKSource == SYSTICK_CLKSOURCE_HCLK) |
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{ |
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SysTick->CTRL |= SYSTICK_CLKSOURCE_HCLK; |
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} |
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else |
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{ |
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SysTick->CTRL &= ~SYSTICK_CLKSOURCE_HCLK; |
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} |
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} |
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/** |
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* @brief This function handles SYSTICK interrupt request. |
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* @retval None |
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*/ |
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void HAL_SYSTICK_IRQHandler(void) |
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{ |
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HAL_SYSTICK_Callback(); |
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} |
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/** |
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* @brief SYSTICK callback. |
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* @retval None |
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*/ |
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__weak void HAL_SYSTICK_Callback(void) |
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{ |
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/* NOTE : This function Should not be modified, when the callback is needed, |
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the HAL_SYSTICK_Callback could be implemented in the user file |
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*/ |
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} |
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/** |
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* @} |
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*/ |
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/** |
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* @} |
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*/ |
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#endif /* HAL_CORTEX_MODULE_ENABLED */ |
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/** |
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* @} |
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*/ |
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/** |
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* @} |
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*/ |
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