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238 lines
9.3 KiB
238 lines
9.3 KiB
/** |
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****************************************************************************** |
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* @file stm32f4xx_hal_sdram.h |
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* @author MCD Application Team |
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* @brief Header file of SDRAM HAL module. |
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****************************************************************************** |
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* @attention |
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* |
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* Copyright (c) 2016 STMicroelectronics. |
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* All rights reserved. |
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* |
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* This software is licensed under terms that can be found in the LICENSE file |
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* in the root directory of this software component. |
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* If no LICENSE file comes with this software, it is provided AS-IS. |
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* |
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****************************************************************************** |
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*/ |
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/* Define to prevent recursive inclusion -------------------------------------*/ |
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#ifndef STM32F4xx_HAL_SDRAM_H |
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#define STM32F4xx_HAL_SDRAM_H |
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#ifdef __cplusplus |
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extern "C" { |
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#endif |
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#if defined(FMC_Bank5_6) |
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/* Includes ------------------------------------------------------------------*/ |
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#include "stm32f4xx_ll_fmc.h" |
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/** @addtogroup STM32F4xx_HAL_Driver |
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* @{ |
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*/ |
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/** @addtogroup SDRAM |
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* @{ |
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*/ |
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/* Exported typedef ----------------------------------------------------------*/ |
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/** @defgroup SDRAM_Exported_Types SDRAM Exported Types |
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* @{ |
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*/ |
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/** |
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* @brief HAL SDRAM State structure definition |
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*/ |
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typedef enum |
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{ |
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HAL_SDRAM_STATE_RESET = 0x00U, /*!< SDRAM not yet initialized or disabled */ |
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HAL_SDRAM_STATE_READY = 0x01U, /*!< SDRAM initialized and ready for use */ |
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HAL_SDRAM_STATE_BUSY = 0x02U, /*!< SDRAM internal process is ongoing */ |
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HAL_SDRAM_STATE_ERROR = 0x03U, /*!< SDRAM error state */ |
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HAL_SDRAM_STATE_WRITE_PROTECTED = 0x04U, /*!< SDRAM device write protected */ |
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HAL_SDRAM_STATE_PRECHARGED = 0x05U /*!< SDRAM device precharged */ |
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} HAL_SDRAM_StateTypeDef; |
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/** |
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* @brief SDRAM handle Structure definition |
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*/ |
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#if (USE_HAL_SDRAM_REGISTER_CALLBACKS == 1) |
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typedef struct __SDRAM_HandleTypeDef |
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#else |
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typedef struct |
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#endif /* USE_HAL_SDRAM_REGISTER_CALLBACKS */ |
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{ |
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FMC_SDRAM_TypeDef *Instance; /*!< Register base address */ |
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FMC_SDRAM_InitTypeDef Init; /*!< SDRAM device configuration parameters */ |
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__IO HAL_SDRAM_StateTypeDef State; /*!< SDRAM access state */ |
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HAL_LockTypeDef Lock; /*!< SDRAM locking object */ |
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DMA_HandleTypeDef *hdma; /*!< Pointer DMA handler */ |
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#if (USE_HAL_SDRAM_REGISTER_CALLBACKS == 1) |
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void (* MspInitCallback)(struct __SDRAM_HandleTypeDef *hsdram); /*!< SDRAM Msp Init callback */ |
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void (* MspDeInitCallback)(struct __SDRAM_HandleTypeDef *hsdram); /*!< SDRAM Msp DeInit callback */ |
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void (* RefreshErrorCallback)(struct __SDRAM_HandleTypeDef *hsdram); /*!< SDRAM Refresh Error callback */ |
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void (* DmaXferCpltCallback)(DMA_HandleTypeDef *hdma); /*!< SDRAM DMA Xfer Complete callback */ |
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void (* DmaXferErrorCallback)(DMA_HandleTypeDef *hdma); /*!< SDRAM DMA Xfer Error callback */ |
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#endif /* USE_HAL_SDRAM_REGISTER_CALLBACKS */ |
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} SDRAM_HandleTypeDef; |
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#if (USE_HAL_SDRAM_REGISTER_CALLBACKS == 1) |
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/** |
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* @brief HAL SDRAM Callback ID enumeration definition |
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*/ |
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typedef enum |
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{ |
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HAL_SDRAM_MSP_INIT_CB_ID = 0x00U, /*!< SDRAM MspInit Callback ID */ |
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HAL_SDRAM_MSP_DEINIT_CB_ID = 0x01U, /*!< SDRAM MspDeInit Callback ID */ |
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HAL_SDRAM_REFRESH_ERR_CB_ID = 0x02U, /*!< SDRAM Refresh Error Callback ID */ |
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HAL_SDRAM_DMA_XFER_CPLT_CB_ID = 0x03U, /*!< SDRAM DMA Xfer Complete Callback ID */ |
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HAL_SDRAM_DMA_XFER_ERR_CB_ID = 0x04U /*!< SDRAM DMA Xfer Error Callback ID */ |
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} HAL_SDRAM_CallbackIDTypeDef; |
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/** |
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* @brief HAL SDRAM Callback pointer definition |
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*/ |
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typedef void (*pSDRAM_CallbackTypeDef)(SDRAM_HandleTypeDef *hsdram); |
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typedef void (*pSDRAM_DmaCallbackTypeDef)(DMA_HandleTypeDef *hdma); |
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#endif /* USE_HAL_SDRAM_REGISTER_CALLBACKS */ |
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/** |
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* @} |
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*/ |
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/* Exported constants --------------------------------------------------------*/ |
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/* Exported macro ------------------------------------------------------------*/ |
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/** @defgroup SDRAM_Exported_Macros SDRAM Exported Macros |
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* @{ |
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*/ |
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/** @brief Reset SDRAM handle state |
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* @param __HANDLE__ specifies the SDRAM handle. |
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* @retval None |
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*/ |
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#if (USE_HAL_SDRAM_REGISTER_CALLBACKS == 1) |
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#define __HAL_SDRAM_RESET_HANDLE_STATE(__HANDLE__) do { \ |
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(__HANDLE__)->State = HAL_SDRAM_STATE_RESET; \ |
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(__HANDLE__)->MspInitCallback = NULL; \ |
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(__HANDLE__)->MspDeInitCallback = NULL; \ |
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} while(0) |
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#else |
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#define __HAL_SDRAM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SDRAM_STATE_RESET) |
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#endif /* USE_HAL_SDRAM_REGISTER_CALLBACKS */ |
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/** |
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* @} |
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*/ |
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/* Exported functions --------------------------------------------------------*/ |
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/** @addtogroup SDRAM_Exported_Functions SDRAM Exported Functions |
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* @{ |
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*/ |
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/** @addtogroup SDRAM_Exported_Functions_Group1 |
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* @{ |
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*/ |
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/* Initialization/de-initialization functions *********************************/ |
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HAL_StatusTypeDef HAL_SDRAM_Init(SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_TimingTypeDef *Timing); |
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HAL_StatusTypeDef HAL_SDRAM_DeInit(SDRAM_HandleTypeDef *hsdram); |
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void HAL_SDRAM_MspInit(SDRAM_HandleTypeDef *hsdram); |
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void HAL_SDRAM_MspDeInit(SDRAM_HandleTypeDef *hsdram); |
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void HAL_SDRAM_IRQHandler(SDRAM_HandleTypeDef *hsdram); |
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void HAL_SDRAM_RefreshErrorCallback(SDRAM_HandleTypeDef *hsdram); |
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void HAL_SDRAM_DMA_XferCpltCallback(DMA_HandleTypeDef *hdma); |
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void HAL_SDRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma); |
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/** |
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* @} |
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*/ |
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/** @addtogroup SDRAM_Exported_Functions_Group2 |
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* @{ |
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*/ |
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/* I/O operation functions ****************************************************/ |
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HAL_StatusTypeDef HAL_SDRAM_Read_8b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint8_t *pDstBuffer, |
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uint32_t BufferSize); |
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HAL_StatusTypeDef HAL_SDRAM_Write_8b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint8_t *pSrcBuffer, |
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uint32_t BufferSize); |
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HAL_StatusTypeDef HAL_SDRAM_Read_16b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint16_t *pDstBuffer, |
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uint32_t BufferSize); |
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HAL_StatusTypeDef HAL_SDRAM_Write_16b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint16_t *pSrcBuffer, |
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uint32_t BufferSize); |
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HAL_StatusTypeDef HAL_SDRAM_Read_32b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pDstBuffer, |
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uint32_t BufferSize); |
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HAL_StatusTypeDef HAL_SDRAM_Write_32b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pSrcBuffer, |
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uint32_t BufferSize); |
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HAL_StatusTypeDef HAL_SDRAM_Read_DMA(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pDstBuffer, |
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uint32_t BufferSize); |
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HAL_StatusTypeDef HAL_SDRAM_Write_DMA(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pSrcBuffer, |
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uint32_t BufferSize); |
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#if (USE_HAL_SDRAM_REGISTER_CALLBACKS == 1) |
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/* SDRAM callback registering/unregistering */ |
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HAL_StatusTypeDef HAL_SDRAM_RegisterCallback(SDRAM_HandleTypeDef *hsdram, HAL_SDRAM_CallbackIDTypeDef CallbackId, |
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pSDRAM_CallbackTypeDef pCallback); |
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HAL_StatusTypeDef HAL_SDRAM_UnRegisterCallback(SDRAM_HandleTypeDef *hsdram, HAL_SDRAM_CallbackIDTypeDef CallbackId); |
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HAL_StatusTypeDef HAL_SDRAM_RegisterDmaCallback(SDRAM_HandleTypeDef *hsdram, HAL_SDRAM_CallbackIDTypeDef CallbackId, |
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pSDRAM_DmaCallbackTypeDef pCallback); |
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#endif /* USE_HAL_SDRAM_REGISTER_CALLBACKS */ |
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/** |
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* @} |
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*/ |
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/** @addtogroup SDRAM_Exported_Functions_Group3 |
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* @{ |
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*/ |
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/* SDRAM Control functions *****************************************************/ |
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HAL_StatusTypeDef HAL_SDRAM_WriteProtection_Enable(SDRAM_HandleTypeDef *hsdram); |
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HAL_StatusTypeDef HAL_SDRAM_WriteProtection_Disable(SDRAM_HandleTypeDef *hsdram); |
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HAL_StatusTypeDef HAL_SDRAM_SendCommand(SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_CommandTypeDef *Command, |
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uint32_t Timeout); |
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HAL_StatusTypeDef HAL_SDRAM_ProgramRefreshRate(SDRAM_HandleTypeDef *hsdram, uint32_t RefreshRate); |
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HAL_StatusTypeDef HAL_SDRAM_SetAutoRefreshNumber(SDRAM_HandleTypeDef *hsdram, uint32_t AutoRefreshNumber); |
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uint32_t HAL_SDRAM_GetModeStatus(SDRAM_HandleTypeDef *hsdram); |
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/** |
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* @} |
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*/ |
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/** @addtogroup SDRAM_Exported_Functions_Group4 |
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* @{ |
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*/ |
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/* SDRAM State functions ********************************************************/ |
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HAL_SDRAM_StateTypeDef HAL_SDRAM_GetState(SDRAM_HandleTypeDef *hsdram); |
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/** |
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* @} |
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*/ |
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/** |
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* @} |
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*/ |
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/** |
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* @} |
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*/ |
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/** |
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* @} |
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*/ |
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#endif /* FMC_Bank5_6 */ |
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#ifdef __cplusplus |
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} |
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#endif |
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#endif /* STM32F4xx_HAL_SDRAM_H */
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